need help in verilog

[malikkhaled]

In my design i have a lot of constants, i want to save these constant in a file and use this file where ever i need it in different modules, but i am getting errors by doing so. anyone could help me here i just post my code.
file name: inc.v

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Code Verilog - [expand]
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`default_nettype none
 
`define k 8
`define k1 32
`define k1 64
`define k1 128
`define k1 256

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in my module i just add it like

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Code Verilog - [expand]
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`include inc.v

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[ads_ee]

try adding "" around the inc.v and path information on where it's located. i.e. `include "../../some_path/inc.v"
for modelsim this path will be relative to the current directory modelsim is running from.

Unless all your files are co-located in the simulation directory it probably won't find the inc.v file otherwise.

Also, you should place the `include inc.v line in your other files outside the module-endmodule structure.

You should also know that including the same inc.v file in a bunch of other files will result in many warnings about redefinition of a define.

I typically use a top level include file which includes all the files (except the top level) including the define file and then the `defines only get defined once.