addition mod m in verilog

[malikkhaled]

i want to do x+y mod m,,using this algorithm
x1= x+y; x2= x1-m;
if x2>=0 then out = x2;
else out =x1;

here is the code...
//////////////////////////////////////
module adder_subtractor ( input [7:0]x, input [7:0]y,output [7:0] out);
parameter m=256;
wire [8:0] x1,x2,c;
assign x1[8:0]= (x[7:0]+y[7:0]);
assign x2[8:0]= (x1[7:0]-m);
or(c,x1[8],x2[8]);
if (c==1'b0)
assign out= x2[7:0];
else
assign out = x1[7:0];

endmodule
/// i have error like c is not a constant,,anyone help me to fix this problem any suggestion

 

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wire [8:0] x1,x2,c;
...
or(c,x1[8],x2[8]);
if (c==1'b0)

You've declared c as a bus.

assign x2[8:0]= (x1[7:0]-m);

m has 9 significant bits 256 == 9'b1_0000_0000
The above code will work but you'll always be subtracting an 8-bit value (zero extended to 9-bits) by a 9-bit value. Are you sure about this?

The value c which you generate by OR'ing the carry bits at first look doesn't seem to be equivalent to the x2>=0 statement in the pseudo code.

 

[qieda]

Hi,

I think in addition you can not use the if

you have to write
assign out = (c==1'b0) ? x1[7:0] : x2[7:0;

or you do it in an always block
e.g.
always@( * ) begin
if (c==1'b0)
out= x2[7:0];
else
out = x1[7:0];
end

regards