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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 1,866
    1st May 2018, 14:19 Go to last post
  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 29,397
    3rd December 2007, 18:00 Go to last post
  1. Poly dummy instead of poly transistor

    Started by Junus2012, Yesterday 22:49
    • Replies: 1
    • Views: 63
    Today, 03:06 Go to last post
  2. Parasatic effect of the dummy transistor

    Started by Junus2012, 21st May 2019 23:33
    • Replies: 9
    • Views: 685
    Yesterday, 15:20 Go to last post
    • Replies: 4
    • Views: 255
    Yesterday, 12:36 Go to last post
  3. Layout of Serial MOSFET

    Started by quyleanh, 20th May 2019 02:55
    • Replies: 1
    • Views: 132
    24th May 2019, 15:59 Go to last post
  4. Capacitive DAC layout in SAR ADC ?

    Started by Electric_Shock, 24th May 2019 15:10
    • Replies: 0
    • Views: 62
    24th May 2019, 15:10 Go to last post
    • Replies: 2
    • Views: 121
    24th May 2019, 13:15 Go to last post
  5. voltage controlled oscilators

    Started by Green_Ic, 21st May 2019 22:02
    • Replies: 2
    • Views: 229
    22nd May 2019, 20:40 Go to last post
  6. Matching of big array transistors

    Started by Junus2012, 21st May 2019 14:14
    • Replies: 3
    • Views: 359
    22nd May 2019, 20:08 Go to last post
  7. [SOLVED] Class AB output stage for VDD=1.8V

    Started by nidare, 19th May 2019 14:04
    • Replies: 3
    • Views: 248
    20th May 2019, 15:50 Go to last post
  8. Common centroid matching array

    Started by Junus2012, 18th May 2019 19:33
    • Replies: 3
    • Views: 557
    20th May 2019, 11:30 Go to last post
  9. Finding Q of Pie matching network

    Started by Chinmaye, 21st January 2019 18:09
    • Replies: 2
    • Views: 1,573
    18th May 2019, 17:38 Go to last post
  10. A zero at folded cascode apmlifier

    Started by shanmei, 14th May 2019 02:19
    • Replies: 6
    • Views: 763
    17th May 2019, 18:10 Go to last post
    • Replies: 4
    • Views: 678
    17th May 2019, 15:47 Go to last post
  11. PMOS input Folded Cascode 0.35Ám

    Started by melkord, 3rd May 2019 23:52
    • Replies: 6
    • Views: 402
    16th May 2019, 21:26 Go to last post
  12. Plotting waveform in Mathlab from Cadence

    Started by Junus2012, 15th May 2019 22:11
    • Replies: 3
    • Views: 566
    16th May 2019, 12:08 Go to last post
  13. TSMC I/O: pad-ESD-core connection

    Started by AllenD, 15th May 2019 22:14
    • Replies: 0
    • Views: 111
    15th May 2019, 22:14 Go to last post
  14. metal fill on the core circuit

    Started by shanmei, 14th May 2019 22:40
    • Replies: 2
    • Views: 985
    15th May 2019, 14:34 Go to last post
  15. IC package company QFP80

    Started by shanmei, 15th May 2019 01:24
    • Replies: 1
    • Views: 553
    15th May 2019, 02:18 Go to last post
  16. Substrate contact vialation

    Started by AllenD, 13th May 2019 03:57
    • Replies: 4
    • Views: 972
    14th May 2019, 21:04 Go to last post
  17. Source degeneration for differential amplifier

    Started by Junus2012, 14th May 2019 14:16
    • Replies: 2
    • Views: 469
    14th May 2019, 19:31 Go to last post
  18. Help Model Generator for cadence layout

    Started by Junus2012, 14th May 2019 14:11
    • Replies: 0
    • Views: 231
    14th May 2019, 14:11 Go to last post
  19. 25G IBM 8HP bicmos quad oscillator design

    Started by the_second, 14th May 2019 09:03
    • Replies: 0
    • Views: 88
    14th May 2019, 09:03 Go to last post
  20. I/O supply and usage

    Started by AllenD, 7th May 2019 06:13
    • Replies: 2
    • Views: 208
    13th May 2019, 13:07 Go to last post
  21. Transient measurements in HSPICE

    Started by rmanalo, 5th May 2019 07:53
    • Replies: 11
    • Views: 1,110
    11th May 2019, 09:34 Go to last post
  22. cadence simulation without schematic view...

    Started by AllenD, 10th May 2019 04:25
    • Replies: 2
    • Views: 601
    10th May 2019, 14:19 Go to last post
    • Replies: 0
    • Views: 176
    9th May 2019, 07:32 Go to last post
  23. Filler cell design (pp layer combination)

    Started by AllenD, 1st May 2019 20:56
    • Replies: 0
    • Views: 282
    1st May 2019, 20:56 Go to last post