Difference between core power pad and IO pad

[RuihW]

Hello everyone,

I'm designing the IO ring with TSMC 0.18um PDK. In my design, the majority of the FETs are 1.8V. But there are some 3V FETs that need 3V for gate (they still use 1.8V for Vds). The 0.18um PDK has two pads: PVDD3A and PVDD3AC. Which one should I use for VDD? My understanding is that since the core is based on 1.8V, I should use 3AC. Am I correct?

 

[rafauy]

What does the documentation say about the A and AC variants? Whats the difference between them?

 

[RuihW]

What does the documentation say about the A and AC variants? Whats the difference between them?

The "C" stands for core. According to the databook, the A variant is for IO voltage (3.3V) and AC is for core voltage (1.8V). After reading the documents, I think I'll use the AC variant for VDD/VSS, and place power-cut cells to isolate the 3V pins.

 

[EV-ffyy]

Hello,

For your design, if the majority of the FETs are 1.8V and you have some 3V FETs that require 3V for the gate while using 1.8V for Vds, you should consider the specific requirements of your design and the characteristics of the pads.

Given that your core voltage is based on 1.8V, using PVDD3AC would be appropriate. The PVDD3AC pad is typically used when you need to interface with core voltages of 1.8V while still providing 3V for specific IO requirements.

 

[dick_freebird]

Sometimes (and especially for analog) you might want to
use 3V FETs and situate them in the core area. The PVDD3AC
might be meant for "Analog" (quiet) core power and PVDD3A
for I/O-ring-located analog pads, where the PVDD3 or PVDD3D
I/O rail must be suspected of being trashy?

Of course I don't know if all N alphasoup permutations are
in the TSMC kit, just speculating - and as designer the choice
is largely yours, although built in inherited connections may
deliver a starting opinion from the logic cell libraries that will
bother you in verification if you pick wrong, to start.