PSRR LDO Measurement

[scottieman]

Dear All,

I found one interesting result from my recent PSRR measurements of a LDO IC.
At light load say 10mA, the measured PSRR around low frequency range (10Hz to 1kHz) is kind of flat. This is same as the prediction from simulation.
At heavy load say 400mA, the measured PSRR around the same low frequency range (10Hz to 1kHz) is not flat. At 10Hz, it is around -50dB and then reduces around the rate of -20dB/dec. This is something I cannot reproduce in the simulation even I include parasitic elements existed on silicon level and PCB level.

Just wonder anyone have similar experience and can share with me your thoughts.

Thanks
Scottie

 

[dick_freebird]

Ar 10mA with headroom the pass FET is in saturation
and at 400mA low headroom it will be in linear region.

Your FET Cgd is a prime factor in PSRR@freq. VIN jerks
the source up while Cgd tries to hold it down, adding
delta Vgs that rises with frequency and opposes the error
amp, degrading the portion of PSRR which comes from
AVOL.

You need a stiff source-referred gate drive that can hold
off the Cgd-coupled "signal", and you do not want to
"enhance" the problem by adding Miller compensation
using capacitance wrapped around the FET. People do
that because Miller gain makes compensation features
more "layout economical".And it can make the Bode plot
look good. If your specs include only DC PSRR you might
even get away with it. Until your customers figure out that
your HF PSRR sucks so bad that the LDO is useless as
a ripple cleaner, and word gets around.