Capacitorless LDO supplies SRAM IP

[MZaher]

Hello All,


As a part of PMU chip design, I am responsible of designing capacitorless LDO which should give the supply to SRAM IP. From my understanding, designing a capacitorless LDO requires a prior knowledge of the load capacitance for proper frequency compensation and hence stability.

The issue is that SRAM IP vendor did not provide any estimations of supply capacitance. Moreover, SRAM includes multiple banks where in one extreme case only one bank is ON (32 kB) and the other extreme case, all banks are ON (2 MB). Therefore, I expect large variations in supply capacitance, is my assumption true? and if this is the case, how do you normally deal with such case?

Are there any reasonable estimations can be made about the supply capacitance from your experience that can ease up my life?

Thank you in advance!

 

[tepalia02]

Simulate the LDO with different load capacitance values to assess its stability and performance across various scenarios. Tools like SPICE simulation can be beneficial in understanding the behavior under different load conditions.

 

[MZaher]

Simulate the LDO with different load capacitance values to assess its stability and performance across various scenarios. Tools like SPICE simulation can be beneficial in understanding the behavior under different load conditions.

Normal capacitorless LDOs are stable by ensuring maximum load capacitance and/or minimum load current (bleed current). I am aware of the limitations of my capacitorless LDO by spice simulations as you have said. My issue is how to estimate SRAM supply capacitance to guarantee that my design lies in the stable region.

 

[D.A.(Tony)Stewart]

The dynamic dV/dt = Ic/C during transitions must then be absorbed by the static C of idle memory.*

Your linear Reg will have a certain open loop Zout and excess gain BW to reduce Zout(f) which is necessary to attenuate dynamic load regulation noise up to GBW.

Your output impedance to dynamic load noise with bias and ESR will determine static and dynamic noise output or "load regulation error and ripple".

*Unless the GBW of your error amp is much greater than you memory speed.

--- Updated Dec 17, 2023 ---

Can SRAM C be estimated from dynamic power using a constant for Coss*RdsOn for SRAM using reference IC's?

--- Updated Dec 17, 2023 ---

may help https://mospace.umsystem.edu/xmlui/...d_umkc_0134D_11675.pdf?sequence=1&isAllowed=y

 

[MZaher]

The dynamic dV/dt = Ic/C during transitions must then be absorbed by the static C of idle memory.*

Your linear Reg will have a certain open loop Zout and excess gain BW to reduce Zout(f) which is necessary to attenuate dynamic load regulation noise up to GBW.

Your output impedance to dynamic load noise with bias and ESR will determine static and dynamic noise output or "load regulation error and ripple".

*Unless the GBW of your error amp is much greater than you memory speed.

--- Updated Dec 17, 2023 ---

Can SRAM C be estimated from dynamic power using a constant for Coss*RdsOn for SRAM using reference IC's?

--- Updated Dec 17, 2023 ---

may help https://mospace.umsystem.edu/xmlui/...d_umkc_0134D_11675.pdf?sequence=1&isAllowed=y

Thank you so much for your response.

I am mainly interested in the load capacitance my LDO will see from SRAM given the large variations in SRAM operation. This will dictate the stability of my LDO.

I would like to see how analog designers here (especially who worked on such designs) were able to make their LDOs stable while driving unknown loads like SRAM or MCU IP.

 

[nitishn5]

Is this the first time this particular SRAM IP was used in your organisation? If not then you need to ask around. There would be data from the previous implementation.
You can probably ask someone doing physical design as they might have the reports of the SRAM and Digital Capacitance from previous implementations.

You might also want to contact the SRAM vendor directly and ask about the capacitance estimates if those are not in the datasheet already.

Also, which process node / foundry are you looking at?

 

[MZaher]

Is this the first time this particular SRAM IP was used in your organisation? If not then you need to ask around. There would be data from the previous implementation.
You can probably ask someone doing physical design as they might have the reports of the SRAM and Digital Capacitance from previous implementations.

You might also want to contact the SRAM vendor directly and ask about the capacitance estimates if those are not in the datasheet already.

Also, which process node / foundry are you looking at?

Thank you so much for your response.

It is TSMC22N.

Yes, it is the first time to be used. No previous data exists at all.

We tried to ask the vendor but there is no clear response unfortunately.

Are there any methods we can do locally to simulate/estimate the real capacitance my LDO will see from SRAM IP?

From my side, I tried to design an LDO that can handle wide range of capacitive unknown loads (100 pF up to more than 10 nF) but I found extreme difficulties to make the LDO stable below 500 pF with load currents below 100 uA --> Ahuja internal loop compensation becomes unstable. Is designing an LDO than can handle this wide range of capacitive loads the right approach to supplying MCU/SRAM IPs? or there are much simpler ways to approach this problem? Please help!

 

[nitishn5]

You have bunch of conditions.
If all SRAM banks along with any Digital remains enabled all the time then you will always see the total capacitance.
If any of the SRAM banks are disabled you should still be seeing the capacitance unless there is any form of power gating.
If there is power gating, then you have the problem of having to be stable to a large range of load capacitance. (Although I can think of a system level solution to this)

One way of estimating, imo, would be to find out the area of one SRAM bank. Then ask the PD/PnR person to implement some chain of inverters or something with that area. And then you can get an estimate of the capacitance of logic gates with that area. But, Logic Gate ≠ SRAM cell.

 

[MZaher]

Thank you again for sharing your thoughts.

I am going to try your suggestion regarding the estimation of the capacitance of one SRAM bank.

In worst case scenario of finding out that my LDO will see large variations in SRAM cap, what is your system level solution for that?
and how do you think of designing an LDO that can cover this wide capacitive variations?

 

[D.A.(Tony)Stewart]

From my side, I tried to design an LDO that can handle wide range of capacitive unknown loads (100 pF up to more than 10 nF) but I found extreme difficulties to make the LDO stable below 500 pF with load currents below 100 uA --> Ahuja internal loop compensation becomes unstable. Is designing an LDO than can handle this wide range of capacitive loads the right approach to supplying MCU/SRAM IPs? or there are much simpler ways to approach this problem? Please help!

At low currents and low ESR load caps, there is insufficient damping, so a tradeoff between ripple rejection and stability requires a range of ESR min:max values.

But I don't understand how it may be called capacitorless if it needs a cap for stability. The example link I posted only needed 1pF for stability but each group of FETs were different. see Table 2

 

[MZaher]

At low currents and low ESR load caps, there is insufficient damping, so a tradeoff between ripple rejection and stability requires a range of ESR min:max values.

But I don't understand how it may be called capacitorless if it needs a cap for stability. The example link I posted only needed 1pF for stability but each group of FETs were different. see Table 2

I mean by "capacitorless" that it only depends on the parasitic capacitance seen from SRAM IP. There is no off-chip cap for this design and hence ESR is of limited concern here.

 

[nitishn5]

One thing to note is that since you are just supplying digital, you don't have to worry too much about the accuracy of your output voltage.
As long as the supply voltage is withing the safe operating limits of the logic/sram, that should be fine.
Which means you don't need super high gain and whatnot.
You can technically go for multiple open loop control. I.e., each SRAM bank can have a separate power transistor (which can also act as a power switch).

Request Rejected

https://www.sciencedirect.com/science/article/abs/pii/S0167926015000036

 

[MZaher]

One thing to note is that since you are just supplying digital, you don't have to worry too much about the accuracy of your output voltage.
As long as the supply voltage is withing the safe operating limits of the logic/sram, that should be fine.
Which means you don't need super high gain and whatnot.
You can technically go for multiple open loop control. I.e., each SRAM bank can have a separate power transistor (which can also act as a power switch).

Request Rejected

https://www.sciencedirect.com/science/article/abs/pii/S0167926015000036

Thank you for your suggestion. I am worried that open loop control may cause large voltage dips during switching. This is why I am thinking of fast transient closed loop designs that can also handle a wide range of capacitive loads and still behave stable.


Did you encounter an LDO design that is unconditionally stable for any load cap? Is that idea feasible at all from your point of view?

 

[nitishn5]

You can do individual FVF loops for each SRAM bank which will provide the fast path and an open loop type for the DC regulation.

For wide range of capacitive loads, you would have to be internally compensated, i.e. the dominant pole is one of the internal poles. This would in turn mean that you are going to be slow which means you would need an alternate fast path if you want to meet any settling specification. From what I have seen, a minimum amount of load cap is placed to ensure that the transient current spikes are not too large and then the LDO provides the rest. ( The Cap averages out current spikes to within the LDO speed ). Technically a source follower type pass stage like an NMOS follower or the FVF should be better since the lower output impedance means that even with a larger load capacitance, your output pole is still far away.

BTW, what is your dropout voltage? Can you use an NMOS or Native NMOS pass transistor?

Check out the below one for an "Any Cap Stable LDO"

https://keep.lib.asu.edu/system/files/c7/60777/tmp/package-OIEe5K/Topp_asu_0010N_11579.pdf

 

[MZaher]

You can do individual FVF loops for each SRAM bank which will provide the fast path and an open loop type for the DC regulation.

For wide range of capacitive loads, you would have to be internally compensated, i.e. the dominant pole is one of the internal poles. This would in turn mean that you are going to be slow which means you would need an alternate fast path if you want to meet any settling specification. From what I have seen, a minimum amount of load cap is placed to ensure that the transient current spikes are not too large and then the LDO provides the rest. ( The Cap averages out current spikes to within the LDO speed ). Technically a source follower type pass stage like an NMOS follower or the FVF should be better since the lower output impedance means that even with a larger load capacitance, your output pole is still far away.

BTW, what is your dropout voltage? Can you use an NMOS or Native NMOS pass transistor?

Check out the below one for an "Any Cap Stable LDO"

https://keep.lib.asu.edu/system/files/c7/60777/tmp/package-OIEe5K/Topp_asu_0010N_11579.pdf

Thank you for your thoughtful replies.


I have given FVF topologies some trials before however I found out that FVF themselves include an internal loop which can go unstable if the load cap is large therefore I do not think FVF is an open loop approach.

Yes, technically FVF and NMOS based LDOs can handle a larger amount of load capacitance however still there is a maximum load cap or/and minimum load current that needs to be ensured so that to guarantee their stability.

I have a limited dropout 200 mV however I have the advantage of using a higher supply for the EA stages before the pass device so I have the option to use NMOS pass device however as I said that its stability is limited to about 1 nF. I need more than 100 uA bleed current to be stable to 5 nF for example.

Regarding the thesis you have attached, as I remember it implements some variant of the Ahuja/indirect compensation and this is what I was trying to design however it requires a large minimum current (1 mA) and also it shows a large undershoot during load transitions.

 

[nitishn5]

If you consider individual Pass stages for each SRAM, then your load cap is not large. It is just unknown (for now).
The FVF loop will provide a fast loop for transient. Since you load is digital, the load regulation need not be accurate.

Consider the Fig3 in the FVF paper I linked above. ere you can have separate FVF stages for each SRAM bank all on the same Vctrl.

 

[MZaher]

If you consider individual Pass stages for each SRAM, then your load cap is not large. It is just unknown (for now).
The FVF loop will provide a fast loop for transient. Since you load is digital, the load regulation need not be accurate.

Consider the Fig3 in the FVF paper I linked above. ere you can have separate FVF stages for each SRAM bank all on the same Vctrl.

Thank you so much!

I think this is a nice system level idea to tackle my problem. I will investigate further into it and get back to you here soon.

From your experience, is it normal in industry to have such uncertainty in the load capacitance of SRAM/MCU IPs? In other words, is the designer normally responsible to deal with such a scenario of unknown load specs?

 

[nitishn5]

From your experience, is it normal in industry to have such uncertainty in the load capacitance of SRAM/MCU IPs? In other words, is the designer normally responsible to deal with such a scenario of unknown load specs?

Tell you boss that you'll need 10mA to keep your design stable with the unknowns and they will come back all the information you need.

Unless you are the boss...!