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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 2,424
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 29,967
    klug
    3rd December 2007, 18:00 Go to last post

  1. Resistance Flicker Noise Question

    Started by lmgrd, 7th August 2019 10:08
    2 Pages •
    1 2
    11 Attachment(s)
    • Replies: 20
    • Views: 793
    pancho_hideboo
    Today, 11:15 Go to last post

  2. Converting drill file in um to mm

    Started by Hawaslsh, Today 02:35
    2 Attachment(s)
    • Replies: 2
    • Views: 61
    Hawaslsh
    Today, 05:06 Go to last post

  3. Calibre Tool for DRC errors

    Started by kingmakerssa, 13th August 2019 15:23
    • Replies: 1
    • Views: 118
    erikl
    Yesterday, 21:25 Go to last post

  4. How to Solve the “Naming Error” in the LVS

    Started by weiTan, 3rd August 2019 06:02
    1 Attachment(s)
    • Replies: 2
    • Views: 177
    tiny_layouter
    18th August 2019, 15:22 Go to last post

  5. calibre LVS missing inductor (bad device detected)

    Started by wypopo, 16th August 2019 19:45
    5 Attachment(s)
    • Replies: 1
    • Views: 159
    dick_freebird
    17th August 2019, 03:35 Go to last post

  6. Biasing of wide swing current mirror

    Started by Junus2012, 4th March 2019 12:37
    4 Attachment(s)
    • Replies: 15
    • Views: 1,014
    sutapanaki
    16th August 2019, 01:08 Go to last post

  7. Decoupling CAP using MOSFET?

    Started by palmeiras, 14th August 2019 17:49
    • Replies: 2
    • Views: 202
    dick_freebird
    14th August 2019, 22:32 Go to last post

  8. Input DC offset result output dc value reach vdd

    Started by SDRookie, 2nd August 2019 05:02
    • Replies: 7
    • Views: 487
    sutapanaki
    14th August 2019, 04:18 Go to last post

  9. Using VCVS as delay elements result in period signal rising and falling time changing

    Started by xianweng, 10th August 2019 17:36
    4 Attachment(s)
    • Replies: 2
    • Views: 310
    dick_freebird
    13th August 2019, 02:14 Go to last post

  10. How to read binary stimulus file in SPECTRE in pwm format

    Started by chj88, 9th August 2019 02:33
    • Replies: 9
    • Views: 336
    chj88
    10th August 2019, 16:51 Go to last post

  11. Why can't extract internal MNA matrices using geometrical description on Hspice

    Started by Saad_imt, 7th August 2019 16:19
    • Replies: 0
    • Views: 105
    Saad_imt
    7th August 2019, 16:19 Go to last post

  12. mosfet as a switch in 28nm technology

    Started by aka_rabbi, 23rd July 2019 06:41
    • Replies: 4
    • Views: 455
    timof
    7th August 2019, 04:51 Go to last post

  13. Simulating VCO Pulling in Cadence

    Started by venn_ng, 5th August 2019 03:09
    1 Attachment(s)
    • Replies: 5
    • Views: 344
    BigBoss
    6th August 2019, 06:30 Go to last post

  14. Problem in using Spectrum Function in Cadence IC6.13

    Started by amr.maghraby, 1st August 2019 13:33
    • Replies: 10
    • Views: 460
    pancho_hideboo
    4th August 2019, 20:57 Go to last post

  15. Error During Cadence CDL Import to Create Schematics

    Started by cadence_ciw_user, 31st July 2019 14:33
    • Replies: 0
    • Views: 200
    cadence_ciw_user
    31st July 2019, 14:33 Go to last post

  16. EKV to BSIM Model Conversion

    Started by Puppet123, 30th July 2019 15:13
    • Replies: 1
    • Views: 207
    vivekroy
    30th July 2019, 18:40 Go to last post

  17. input current of the integrator

    Started by shanmei, 26th July 2019 14:30
    1 Attachment(s)
    • Replies: 15
    • Views: 805
    asdf44
    29th July 2019, 20:06 Go to last post

  18. Deep nwell connection

    Started by vsupadhya, 19th July 2019 07:20
    • Replies: 6
    • Views: 528
    Alexxk
    29th July 2019, 06:59 Go to last post

  19. How to measure the input reactance and output reactance of a MOSFET/gain stage

    Started by circuitking, 26th July 2019 08:39
    1 Attachment(s)
    • Replies: 7
    • Views: 483
    vivekroy
    27th July 2019, 17:26 Go to last post

  20. Nand gate using bsim-cmg

    Started by neku, 15th July 2019 17:36
    • Replies: 1
    • Views: 260
    erikl
    26th July 2019, 16:10 Go to last post

  21. Questions in manually creating substrate files for Sonnet Cadence Interface

    Started by JLHW, 25th July 2019 17:38
    • Replies: 0
    • Views: 251
    JLHW
    25th July 2019, 17:38 Go to last post

  22. PCB designing and wire bonding both

    Started by ICdesignerbeginner, 24th June 2019 07:11
    • Replies: 2
    • Views: 294
    ThisIsNotSam
    24th July 2019, 17:15 Go to last post

  23. [SOLVED] Need RF examples lib.

    Started by Nancy12345, 23rd July 2019 04:30
    • Replies: 4
    • Views: 283
    Nancy12345
    24th July 2019, 02:20 Go to last post

  24. sfdr simulation in Matlab

    Started by shanmei, 9th July 2019 15:38
    2 Attachment(s)
    • Replies: 1
    • Views: 286
    Puppet123
    24th July 2019, 01:13 Go to last post

  25. LC VCO with Capacitor filter, what is the cap doing?

    Started by mvj, 17th June 2019 11:37
    1 Attachment(s)
    • Replies: 6
    • Views: 551
    saro_k_82
    23rd July 2019, 18:18 Go to last post

  26. What's the difference between stacked and cascode configurations?

    Started by circuitking, 20th July 2019 21:48
    2 Attachment(s)
    • Replies: 5
    • Views: 442
    circuitking
    23rd July 2019, 13:41 Go to last post

  27. DRC and LVS in Calibre

    Started by Ata-Va, 20th July 2019 00:17
    • Replies: 2
    • Views: 401
    slizak
    22nd July 2019, 16:58 Go to last post

  28. Mixed Signal IC Grounds

    Started by Alexxk, 25th June 2019 12:03
    • Replies: 7
    • Views: 609
    vivekroy
    22nd July 2019, 06:55 Go to last post

  29. Op-amp and compensation

    Started by venn_ng, 3rd June 2019 03:22
    1 Attachment(s)
    • Replies: 4
    • Views: 544
    saro_k_82
    21st July 2019, 15:52 Go to last post

  30. DNL/INL Using Cadence ahdlLib blocks

    Started by Puppet123, 21st July 2019 01:06
    • Replies: 0
    • Views: 186
    Puppet123
    21st July 2019, 01:40 Go to last post
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