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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 7,009
    1st May 2018, 14:19 Go to last post
  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 34,595
    3rd December 2007, 18:00 Go to last post
  1. Rail to rail circuit simulation

    Started by ibiteee, 19th May 2020 15:35
    • Replies: 10
    • Views: 545
    Yesterday, 22:14 Go to last post
    • Replies: 5
    • Views: 337
    Yesterday, 20:04 Go to last post
    • Replies: 6
    • Views: 232
    Yesterday, 19:26 Go to last post
  2. Schematic circuit plot from Cadence Virtuoso

    Started by Junus2012, 31st May 2020 17:35
    • Replies: 10
    • Views: 245
    Yesterday, 16:34 Go to last post
  3. Link between sampling and accuracy

    Started by yefj, 26th May 2020 14:28
    • Replies: 3
    • Views: 378
    30th May 2020, 01:43 Go to last post
  4. Noise simulation of OPAmp

    Started by deep_sea, 28th May 2020 05:26
    • Replies: 2
    • Views: 253
    29th May 2020, 09:36 Go to last post
    • Replies: 2
    • Views: 968
    29th May 2020, 03:17 Go to last post
  5. Circuit Design using FinFETs

    Started by nidish, 25th May 2020 16:32
    • Replies: 2
    • Views: 181
    26th May 2020, 05:28 Go to last post
  6. Time Interleaved ADC Filtering at Output

    Started by Puppet123, 23rd May 2020 22:40
    • Replies: 3
    • Views: 374
    24th May 2020, 23:13 Go to last post
    • Replies: 8
    • Views: 420
    23rd May 2020, 21:47 Go to last post
  7. Bulk fixing (gluing) CMOS

    Started by lufer17, 23rd May 2020 14:49
    • Replies: 1
    • Views: 208
    23rd May 2020, 18:46 Go to last post
  8. Verilog and VHDL noise modelling

    Started by deep_sea, 20th May 2020 12:28
    • Replies: 5
    • Views: 416
    22nd May 2020, 11:14 Go to last post
  9. The stability of the power amplifier

    Started by OZZAA, 5th April 2020 08:01
    • Replies: 3
    • Views: 546
    20th May 2020, 01:01 Go to last post
    • Replies: 3
    • Views: 310
    19th May 2020, 10:13 Go to last post
    • Replies: 11
    • Views: 879
    16th May 2020, 09:07 Go to last post
  10. Trends in Analog IP for ASIC Design

    Started by JElectric, 6th May 2020 12:46
    • Replies: 7
    • Views: 722
    15th May 2020, 23:44 Go to last post
  11. Layout of big transistors

    Started by Junus2012, 14th May 2020 23:19
    • Replies: 3
    • Views: 343
    15th May 2020, 18:31 Go to last post
    • Replies: 12
    • Views: 974
    15th May 2020, 10:52 Go to last post
    • Replies: 11
    • Views: 855
    14th May 2020, 23:40 Go to last post
  12. Matching the biasing circuit to the core amplifier

    Started by Junus2012, 2nd May 2020 22:07
    2 Pages
    1 2
    • Replies: 20
    • Views: 2,034
    13th May 2020, 17:39 Go to last post
    • Replies: 7
    • Views: 1,632
    13th May 2020, 10:39 Go to last post
  13. SAR ADC Architecture Blocks

    Started by Adithya_Pai, 1st May 2020 19:40
    • Replies: 5
    • Views: 1,284
    9th May 2020, 18:46 Go to last post
  14. Is this CMRR plot correct?

    Started by fat_123, 7th May 2020 21:19
    • Replies: 3
    • Views: 450
    9th May 2020, 13:32 Go to last post
    • Replies: 10
    • Views: 1,448
    9th May 2020, 12:05 Go to last post
  15. CMOS differential OPAmp

    Started by MILIND_7, 18th March 2020 10:53
    • Replies: 5
    • Views: 715
    9th May 2020, 10:13 Go to last post
  16. Level converter devices

    Started by joniengr, 8th May 2020 08:24
    • Replies: 1
    • Views: 216
    8th May 2020, 08:52 Go to last post
  17. Cascoding the two stage folded class AB ampliifer

    Started by Junus2012, 28th March 2020 17:31
    2 Pages
    1 2
    • Replies: 21
    • Views: 3,429
    7th May 2020, 21:59 Go to last post