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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 1,996
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 29,534
    klug
    3rd December 2007, 18:00 Go to last post

  1. CMRR is less than the DC differential gain

    Started by Junus2012, 17th June 2019 18:24
    • Replies: 10
    • Views: 271
    Dominik Przyborowski
    Yesterday, 20:06 Go to last post

  2. Op-amp design specification for certain application

    Started by Junus2012, Yesterday 13:20
    1 Attachment(s)
    • Replies: 5
    • Views: 111
    sutapanaki
    Yesterday, 17:53 Go to last post

  3. Mixed Signal IC Grounds

    Started by Alexxk, Yesterday 12:03
    • Replies: 0
    • Views: 43
    Alexxk
    Yesterday, 12:03 Go to last post

  4. Different connections to Common node in differential pair

    Started by circuitking, 24th June 2019 18:59
    1 Attachment(s)
    • Replies: 4
    • Views: 104
    BradtheRad
    Yesterday, 03:43 Go to last post

  5. stretching the 0 pulse of a digital output with a certain T

    Started by iaf, 14th June 2019 14:01
    4 Attachment(s)
    • Replies: 18
    • Views: 515
    iaf
    24th June 2019, 13:50 Go to last post

  6. PCB designing and wire bonding both

    Started by ICdesignerbeginner, 24th June 2019 07:11
    • Replies: 0
    • Views: 57
    ICdesignerbeginner
    24th June 2019, 07:11 Go to last post

  7. Looking for 'Introduction to CMOS OP-AMPs and Comparators' ebook

    Started by hobbyiclearner, 23rd June 2019 20:05
    • Replies: 1
    • Views: 83
    dick_freebird
    23rd June 2019, 23:37 Go to last post

  8. Half Bridge driver veriloga model

    Started by michelebergo, 22nd June 2019 10:38
    • Replies: 0
    • Views: 101
    michelebergo
    22nd June 2019, 10:38 Go to last post

  9. Cadence 6.1.4 on CentOS (***** cadence)

    Started by Majid_Vatan_Parast, 21st June 2019 07:57
    1 Attachment(s)
    • Replies: 0
    • Views: 91
    Majid_Vatan_Parast
    21st June 2019, 07:57 Go to last post

  10. Analog Layout - Multipliers and Fingers

    Started by Puppet123, 21st June 2019 02:40
    • Replies: 1
    • Views: 103
    dick_freebird
    21st June 2019, 03:02 Go to last post

  11. Opamp Layout Example

    Started by Puppet123, 19th June 2019 18:05
    • Replies: 1
    • Views: 155
    BradtheRad
    20th June 2019, 05:32 Go to last post

  12. TSMC 65nm mocap_rf varactor

    Started by mahir, 18th June 2019 15:02
    • Replies: 1
    • Views: 153
    frankrose
    18th June 2019, 23:27 Go to last post

  13. "calibre view generation encountered a fatal error" but spectre PEX extraction works

    Started by OG_, 11th June 2019 15:48
    4 Attachment(s)
    • Replies: 12
    • Views: 720
    OG_
    18th June 2019, 21:12 Go to last post

  14. LC VCO with Capacitor filter, what is the cap doing?

    Started by mvj, 17th June 2019 11:37
    1 Attachment(s)
    • Replies: 2
    • Views: 170
    mvj
    18th June 2019, 14:31 Go to last post

  15. [SOLVED] measuring the parasitic capacitance at a certain node in cadence

    Started by amr.maghraby, 17th June 2019 14:23
    • Replies: 7
    • Views: 221
    ThisIsNotSam
    17th June 2019, 20:47 Go to last post

  16. Mismatch Contribution Analysis

    Started by rosaeidi, 17th June 2019 17:26
    • Replies: 1
    • Views: 105
    frankrose
    17th June 2019, 18:43 Go to last post

  17. PMOS WELL of same bulk potential of different transistor groups

    Started by Junus2012, 11th June 2019 17:41
    • Replies: 5
    • Views: 296
    sutapanaki
    13th June 2019, 00:37 Go to last post

  18. layout connection using different metalization layers

    Started by Junus2012, 11th June 2019 14:10
    • Replies: 7
    • Views: 243
    Junus2012
    12th June 2019, 23:03 Go to last post

  19. Port size in layout design

    Started by Junus2012, 11th June 2019 16:00
    • Replies: 4
    • Views: 192
    Junus2012
    12th June 2019, 23:01 Go to last post

  20. current mirror matching issue

    Started by Junus2012, 9th June 2019 18:55
    1 Attachment(s)
    • Replies: 7
    • Views: 325
    Junus2012
    12th June 2019, 22:49 Go to last post

  21. gate connection using poly vs metal

    Started by Junus2012, 9th June 2019 19:19
    1 Attachment(s)
    • Replies: 5
    • Views: 319
    dick_freebird
    11th June 2019, 23:15 Go to last post

  22. Drai and source via contact

    Started by Junus2012, 11th June 2019 14:01
    • Replies: 1
    • Views: 117
    Dominik Przyborowski
    11th June 2019, 20:40 Go to last post

  23. guard ring contacts for the PMOS transistors

    Started by Junus2012, 11th June 2019 13:59
    • Replies: 1
    • Views: 105
    ljp2706
    11th June 2019, 16:17 Go to last post

  24. Layout Abutment Sitting in the TSMC PDK

    Started by JAVAD_B, 11th June 2019 09:46
    1 Attachment(s)
    • Replies: 3
    • Views: 174
    ljp2706
    11th June 2019, 16:11 Go to last post

  25. TSMC 65nm Inductor Finder Parameters

    Started by mahir, 10th June 2019 15:21
    • Replies: 2
    • Views: 132
    mahir
    11th June 2019, 08:25 Go to last post

  26. Run Veriloga demo in hspice 2013.03-SP2 error

    Started by yyy963741tw, 11th June 2019 08:19
    2 Attachment(s)
    • Replies: 0
    • Views: 104
    yyy963741tw
    11th June 2019, 08:19 Go to last post

  27. [SOLVED] How to calculate the input-refered noise for two OTA in parallel?

    Started by nidare, 9th June 2019 16:43
    • Replies: 4
    • Views: 285
    nidare
    10th June 2019, 11:41 Go to last post

  28. Plotting waveform in Mathlab from Cadence

    Started by Junus2012, 15th May 2019 22:11
    • Replies: 5
    • Views: 1,041
    ljp2706
    9th June 2019, 22:04 Go to last post

  29. Pin definition in TSMC 0.18um

    Started by JAVAD_B, 7th June 2019 14:15
    • Replies: 4
    • Views: 300
    JAVAD_B
    9th June 2019, 07:46 Go to last post

  30. devideing large MOSFET gate using muti fingers

    Started by Junus2012, 7th June 2019 18:05
    • Replies: 4
    • Views: 241
    Dominik Przyborowski
    8th June 2019, 23:39 Go to last post
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