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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 2,650
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 30,194
    klug
    3rd December 2007, 18:00 Go to last post

  1. ConnectLib files in ams simulation Cadence

    Started by Chinmaye, Yesterday 19:19
    • Replies: 0
    • Views: 59
    Chinmaye
    Yesterday, 19:19 Go to last post

  2. Combine circuit and Verilog in Cadence

    Started by Chinmaye, 14th September 2019 18:09
    • Replies: 1
    • Views: 155
    Dominik Przyborowski
    14th September 2019, 18:30 Go to last post

  3. What is the difference between LVS and ERC ?

    Started by MubarakKhan, 13th September 2019 11:36
    • Replies: 1
    • Views: 120
    erikl
    13th September 2019, 18:15 Go to last post

  4. Problems in Verifying Silterra Library Cells using Calibre

    Started by JLHW, 13th September 2019 17:12
    1 Attachment(s)
    • Replies: 0
    • Views: 72
    JLHW
    13th September 2019, 17:12 Go to last post

  5. Verilog-a code to latch analog voltages

    Started by Chinmaye, 11th September 2019 07:11
    1 Attachment(s)
    • Replies: 7
    • Views: 246
    vivekroy
    12th September 2019, 19:51 Go to last post

  6. DNL/INL Measurement in Cadence for DAC

    Started by Puppet123, 12th September 2019 01:45
    • Replies: 2
    • Views: 184
    Dominik Przyborowski
    12th September 2019, 04:44 Go to last post

  7. INL/DNL Measurement from Cadence Spectre/Virtuoso Output

    Started by Puppet123, 6th September 2019 21:44
    • Replies: 7
    • Views: 377
    pancho_hideboo
    12th September 2019, 01:32 Go to last post

  8. Verilog-a code for differential amplifier

    Started by Chinmaye, 11th September 2019 07:20
    • Replies: 4
    • Views: 163
    Chinmaye
    11th September 2019, 18:49 Go to last post

  9. Current reference design for CS-DAC

    Started by Shishira, 6th September 2019 19:07
    1 Attachment(s)
    • Replies: 5
    • Views: 289
    Dominik Przyborowski
    11th September 2019, 06:07 Go to last post

  10. How to change the m factor (multiplication factor) for Instances in cadence

    Started by Junus2012, 26th August 2019 19:31
    1 Attachment(s)
    • Replies: 5
    • Views: 249
    Dominik Przyborowski
    10th September 2019, 20:12 Go to last post

  11. Differential and common mode input resistance of the fully diffferential amplifier

    Started by Junus2012, 2nd September 2019 13:17
    8 Attachment(s)
    • Replies: 19
    • Views: 637
    Junus2012
    10th September 2019, 19:36 Go to last post

  12. Charge pump topology

    Started by bharath_k, 5th September 2019 11:44
    2 Attachment(s)
    • Replies: 4
    • Views: 530
    bharath_k
    9th September 2019, 09:42 Go to last post

  13. ADE-XL: 2 tests have a same variable but it is constant for test1 and swept for tes2

    Started by circuitking, 9th September 2019 01:56
    • Replies: 1
    • Views: 164
    Dominik Przyborowski
    9th September 2019, 04:46 Go to last post

  14. W/L of pMOS and nMOS of CD4007 Chip.

    Started by vijender13, 6th September 2019 06:20
    • Replies: 3
    • Views: 215
    frankrose
    8th September 2019, 22:24 Go to last post

  15. Generate pulses of different widths

    Started by Chinmaye, 8th September 2019 10:20
    • Replies: 1
    • Views: 134
    erikl
    8th September 2019, 20:21 Go to last post

  16. Error and Questions related to Calibre 2015 in Cadence

    Started by JLHW, 8th September 2019 18:22
    2 Attachment(s)
    • Replies: 0
    • Views: 125
    JLHW
    8th September 2019, 18:22 Go to last post

  17. Changing the 'VSS' value in CppSim

    Started by vivekroy, 8th September 2019 14:04
    • Replies: 0
    • Views: 123
    vivekroy
    8th September 2019, 14:04 Go to last post

  18. Help on Ocean scripting: run one analysis and use that results in another

    Started by circuitking, 6th September 2019 21:59
    • Replies: 8
    • Views: 338
    vivekroy
    8th September 2019, 13:37 Go to last post

  19. Factors deciding Silicon Wafer Thickness

    Started by Vishu21_95, 29th August 2019 06:53
    • Replies: 2
    • Views: 218
    dick_freebird
    5th September 2019, 02:22 Go to last post

  20. Interdigitation techniques when working with FinFETs

    Started by mamir, 4th September 2019 20:59
    • Replies: 0
    • Views: 127
    mamir
    4th September 2019, 20:59 Go to last post

  21. Deaign of low ON resistor CMOS transmission gate

    Started by Junus2012, 17th April 2019 12:26
    1 Attachment(s)
    • Replies: 18
    • Views: 4,095
    dick_freebird
    4th September 2019, 04:18 Go to last post

  22. LVS Subtype error at layout

    Started by rty94, 28th August 2019 22:23
    • Replies: 2
    • Views: 292
    k_90
    3rd September 2019, 16:00 Go to last post

  23. Inverters as Level Shifter with HVT and LVT transistors

    Started by john.zhang, 3rd September 2019 04:37
    • Replies: 3
    • Views: 370
    vivekroy
    3rd September 2019, 10:39 Go to last post

  24. How to differentiate offset voltage error from CMRR and PSRR

    Started by Junus2012, 2nd September 2019 17:16
    1 Attachment(s)
    • Replies: 4
    • Views: 187
    Junus2012
    3rd September 2019, 10:23 Go to last post

  25. CMRR at different closed loop gain

    Started by Junus2012, 2nd September 2019 12:32
    • Replies: 5
    • Views: 438
    FvM
    3rd September 2019, 08:01 Go to last post

  26. Resistance Flicker Noise Question

    Started by lmgrd, 7th August 2019 10:08
    2 Pages •
    1 2
    11 Attachment(s)
    • Replies: 21
    • Views: 1,287
    pancho_hideboo
    1st September 2019, 14:20 Go to last post

  27. How to measure the input reactance and output reactance of a MOSFET/gain stage

    Started by circuitking, 26th July 2019 08:39
    1 Attachment(s)
    • Replies: 8
    • Views: 800
    circuitking
    31st August 2019, 12:25 Go to last post

  28. ramp generation using switched cap integrator

    Started by Chinmaye, 30th August 2019 11:08
    • Replies: 3
    • Views: 285
    Easy peasy
    30th August 2019, 20:57 Go to last post

  29. Standard Cells Library Silicon Validation

    Started by tok47, 30th August 2019 08:33
    • Replies: 0
    • Views: 146
    tok47
    30th August 2019, 08:33 Go to last post

  30. Phase Noise Spurs in simulation of clock distribution circuit

    Started by wsamples01, 29th August 2019 21:41
    1 Attachment(s)
    • Replies: 0
    • Views: 144
    wsamples01
    29th August 2019, 21:41 Go to last post
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