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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 1,248
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 29,148
    klug
    3rd December 2007, 18:00 Go to last post

  1. Settling time simulation for the operational amplifier in Cadence

    Started by Junus2012, Yesterday 19:30
    3 Attachment(s)
    • Replies: 4
    • Views: 71
    dick_freebird
    Yesterday, 22:41 Go to last post

  2. Output Resistance of Amplifier with Feedback ( Series - shunt) Loading

    Started by Robotduck, 21st April 2019 18:03
    1 Attachment(s)
    • Replies: 4
    • Views: 178
    LvW
    Yesterday, 11:08 Go to last post

  3. Offset nonlinearity of Rail-to-Rail OpAmp

    Started by ICnow, 19th April 2019 14:36
    • Replies: 6
    • Views: 625
    dick_freebird
    22nd April 2019, 21:15 Go to last post

  4. Error in Monte Carlo and Process Corner Simulations on Cadence

    Started by Shanelle09, 22nd April 2019 06:57
    • Replies: 0
    • Views: 76
    Shanelle09
    22nd April 2019, 06:57 Go to last post

  5. Deaign of low ON resistor CMOS transmission gate

    Started by Junus2012, 17th April 2019 12:26
    1 Attachment(s)
    • Replies: 15
    • Views: 1,366
    Junus2012
    21st April 2019, 21:30 Go to last post

  6. Modeling 5th order CTSD in VerilogA

    Started by RamyRady_RF, 21st April 2019 02:00
    • Replies: 1
    • Views: 221
    pancho_hideboo
    21st April 2019, 05:00 Go to last post

  7. Worst case Corner Analyses in Cadence

    Started by Junus2012, 10th April 2019 11:33
    2 Pages •
    1 2
    2 Attachment(s)
    • Replies: 21
    • Views: 2,759
    sutapanaki
    19th April 2019, 20:55 Go to last post

  8. Difference between 180nm and 130nm with same W/L ratio

    Started by jaydnul, 17th April 2019 23:31
    • Replies: 3
    • Views: 216
    dick_freebird
    18th April 2019, 22:12 Go to last post

  9. [SOLVED] Signal Ground attached to my DC bias ground?

    Started by Hawaslsh, 16th April 2019 00:09
    9 Attachment(s)
    • Replies: 15
    • Views: 438
    KlausST
    18th April 2019, 16:08 Go to last post

  10. Resources to learn about silicon photonics IC design

    Started by RamyRady_RF, 17th April 2019 12:48
    • Replies: 0
    • Views: 98
    RamyRady_RF
    17th April 2019, 12:48 Go to last post

  11. Input common mode range simulation for fully differential amplifier

    Started by Junus2012, 2nd April 2019 11:20
    1 Attachment(s)
    • Replies: 7
    • Views: 888
    Junus2012
    16th April 2019, 22:23 Go to last post

  12. [SOLVED] Frequency compensation using Null resistor

    Started by Robotduck, 16th April 2019 19:49
    1 Attachment(s)
    • Replies: 1
    • Views: 144
    vivekroy
    16th April 2019, 21:18 Go to last post

  13. Zero diagonal found in Jacobian error in simulation the DAC?

    Started by Electric_Shock, 16th April 2019 07:17
    2 Attachment(s)
    • Replies: 2
    • Views: 148
    dick_freebird
    16th April 2019, 20:49 Go to last post

  14. [SOLVED] Power Supply Rejection Ratio

    Started by Robotduck, 16th April 2019 16:08
    • Replies: 1
    • Views: 177
    KlausST
    16th April 2019, 16:27 Go to last post

  15. Create a long delay with using inverter gate?

    Started by Electric_Shock, 10th April 2019 13:13
    1 Attachment(s)
    • Replies: 10
    • Views: 388
    sutapanaki
    14th April 2019, 21:25 Go to last post

  16. Simulating Mos varctor

    Started by Gurjar, 13th April 2019 11:11
    • Replies: 1
    • Views: 132
    frankrose
    14th April 2019, 09:41 Go to last post

  17. MOSFET diode connected for biasing

    Started by Junus2012, 4th April 2019 16:59
    5 Attachment(s)
    • Replies: 9
    • Views: 1,131
    Junus2012
    13th April 2019, 13:59 Go to last post

  18. UHF RFID Chip impedance with 50 ohm

    Started by shanmei, 19th January 2019 21:23
    • Replies: 9
    • Views: 1,077
    vivekroy
    13th April 2019, 11:05 Go to last post

  19. Verilog-A $Strobe statement display in virtuoso

    Started by MahmoudHassan, 10th April 2019 17:55
    1 Attachment(s)
    • Replies: 1
    • Views: 186
    pancho_hideboo
    11th April 2019, 05:43 Go to last post

  20. Help in Verilog-A with cadence virtuoso

    Started by MahmoudHassan, 5th April 2019 17:58
    1 Attachment(s)
    • Replies: 10
    • Views: 1,233
    pancho_hideboo
    11th April 2019, 05:27 Go to last post

  21. [moved] ZnO solution/Drop casting

    Started by Melina2018, 10th April 2019 06:59
    • Replies: 0
    • Views: 98
    Melina2018
    10th April 2019, 06:59 Go to last post

  22. LVS failed issue - Cannot Find Switch Cells...

    Started by jylei, 9th April 2019 22:54
    • Replies: 0
    • Views: 126
    jylei
    9th April 2019, 22:54 Go to last post

  23. Monticarlo Analyses in Cadence

    Started by Junus2012, 6th April 2019 23:29
    2 Pages •
    1 2
    3 Attachment(s)
    • Replies: 22
    • Views: 2,506
    Junus2012
    9th April 2019, 19:07 Go to last post

  24. How to find formula of calculating resistance in Pcell?

    Started by quyleanh, 9th April 2019 13:35
    • Replies: 2
    • Views: 143
    Dominik Przyborowski
    9th April 2019, 18:23 Go to last post

  25. Post layout simulation results differ from prelayout simulation- S21 is negative

    Started by sp.bhuvana, 2nd April 2019 05:59
    2 Attachment(s)
    • Replies: 7
    • Views: 963
    sp.bhuvana
    9th April 2019, 10:41 Go to last post

  26. Effect of Gds on Gain

    Started by shruthi08, 20th March 2019 17:14
    4 Attachment(s)
    • Replies: 12
    • Views: 1,939
    sutapanaki
    9th April 2019, 07:00 Go to last post

  27. Layout related issues: ground scheme, bias current

    Started by AllenD, 7th April 2019 07:59
    • Replies: 2
    • Views: 349
    vivekroy
    7th April 2019, 13:54 Go to last post

  28. AC / Noise after a tran

    Started by Fabien, 5th April 2019 10:28
    • Replies: 3
    • Views: 244
    FvM
    7th April 2019, 08:46 Go to last post

  29. Verilog-A platform for windows

    Started by MahmoudHassan, 5th April 2019 17:51
    • Replies: 1
    • Views: 254
    pancho_hideboo
    6th April 2019, 16:57 Go to last post

  30. Current in bulk cascode device

    Started by maxporter, 4th April 2019 16:07
    1 Attachment(s)
    • Replies: 2
    • Views: 228
    maxporter
    4th April 2019, 22:18 Go to last post
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