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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 2,140
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 29,684
    klug
    3rd December 2007, 18:00 Go to last post

  1. What if fin width of finfet will adjust..

    Started by santoshraghu456, Today 08:25
    • Replies: 0
    • Views: 51
    santoshraghu456
    Today, 08:25 Go to last post

  2. Why we should choose even number of finger

    Started by quyleanh, 10th July 2019 05:30
    • Replies: 7
    • Views: 337
    quyleanh
    Today, 06:33 Go to last post

  3. MOSFET Speed and power tradeoff

    Started by circuitking, Yesterday 10:45
    • Replies: 1
    • Views: 87
    avadak
    Today, 06:33 Go to last post

  4. Zero threshold MOSFET design

    Started by decaf14, Yesterday 22:13
    • Replies: 1
    • Views: 95
    dick_freebird
    Today, 00:43 Go to last post

  5. Nand gate using bsim-cmg

    Started by neku, Yesterday 17:36
    • Replies: 0
    • Views: 56
    neku
    Yesterday, 17:36 Go to last post

  6. Mixed Signal IC Grounds

    Started by Alexxk, 25th June 2019 12:03
    • Replies: 1
    • Views: 167
    kripacharya
    13th July 2019, 21:08 Go to last post

  7. Masking and non-masking the alphabet and numbers on the top side of fabricated chip.

    Started by issacchook, 27th June 2019 05:29
    • Replies: 1
    • Views: 157
    kripacharya
    13th July 2019, 21:03 Go to last post

  8. Best books for Current mirrors and differential amplifiers using MOSFFET

    Started by circuitking, 11th July 2019 23:28
    • Replies: 4
    • Views: 255
    circuitking
    12th July 2019, 13:31 Go to last post

  9. The issue of Assura LVS

    Started by l.kim, 12th July 2019 08:36
    • Replies: 1
    • Views: 113
    rangermad
    12th July 2019, 13:03 Go to last post

  10. "calibre view generation encountered a fatal error" but spectre PEX extraction works

    Started by OG_, 11th June 2019 15:48
    4 Attachment(s)
    • Replies: 13
    • Views: 1,080
    ljp2706
    12th July 2019, 00:38 Go to last post

  11. Update schematic regarding layout

    Started by hannover90, 9th July 2019 19:14
    • Replies: 1
    • Views: 242
    strotta
    10th July 2019, 11:42 Go to last post

  12. sfdr simulation in Matlab

    Started by shanmei, 9th July 2019 15:38
    2 Attachment(s)
    • Replies: 0
    • Views: 128
    shanmei
    9th July 2019, 15:38 Go to last post

  13. Looking for 'Introduction to CMOS OP-AMPs and Comparators' ebook

    Started by hobbyiclearner, 23rd June 2019 20:05
    • Replies: 10
    • Views: 501
    timof
    9th July 2019, 00:53 Go to last post

  14. Understanding the inversion coefficient proposed by EKV

    Started by Alex Liao, 5th July 2019 16:02
    • Replies: 2
    • Views: 316
    Alex Liao
    8th July 2019, 15:42 Go to last post

  15. How Device Resistance change with respect to W and L in any technoogy

    Started by circuitking, 7th July 2019 09:17
    2 Attachment(s)
    • Replies: 2
    • Views: 286
    pancho_hideboo
    7th July 2019, 15:41 Go to last post

  16. Comparator characterization for variable input

    Started by iaf, 4th July 2019 14:31
    • Replies: 6
    • Views: 283
    KlausST
    4th July 2019, 22:08 Go to last post

  17. Difference between S3 and T3 Layer used in 22FDX Technology

    Started by Vishu21_95, 4th July 2019 12:41
    • Replies: 0
    • Views: 136
    Vishu21_95
    4th July 2019, 12:41 Go to last post

  18. Why is pmos and nmos put vertically and not side by side(horizontally)in ic layouts?

    Started by 94d33m, 2nd July 2019 18:18
    • Replies: 6
    • Views: 372
    Vishu21_95
    3rd July 2019, 15:06 Go to last post

  19. [SOLVED] Use of hybrid layer in devices

    Started by Vishu21_95, 1st July 2019 05:58
    • Replies: 3
    • Views: 245
    dr_kca
    2nd July 2019, 11:47 Go to last post

  20. Learning to write code for circuit design, where to start?

    Started by circuitking, 27th June 2019 19:07
    • Replies: 2
    • Views: 343
    nitishn5
    1st July 2019, 07:49 Go to last post

  21. Error: Net width does not match instance/terminal width during calibre Pex

    Started by ahmed.reda.mohamed, 30th June 2019 06:34
    1 Attachment(s)
    • Replies: 1
    • Views: 155
    vivekroy
    30th June 2019, 22:03 Go to last post

  22. Different connections to Common node in differential pair

    Started by circuitking, 24th June 2019 18:59
    1 Attachment(s)
    • Replies: 5
    • Views: 338
    circuitking
    27th June 2019, 18:42 Go to last post

  23. Op-amp design specification for certain application

    Started by Junus2012, 25th June 2019 13:20
    1 Attachment(s)
    • Replies: 7
    • Views: 379
    barry
    27th June 2019, 18:26 Go to last post

  24. 3-bit Delta-Sigma Modulator in Verilog-A

    Started by JoZwo, 27th June 2019 16:54
    • Replies: 0
    • Views: 97
    JoZwo
    27th June 2019, 16:54 Go to last post

  25. when calculating the SNR of adc，should the bandwidth of noise be 1/2fsample？

    Started by alex_fd, 26th June 2019 23:20
    • Replies: 2
    • Views: 161
    KlausST
    27th June 2019, 06:05 Go to last post

  26. CMRR is less than the DC differential gain

    Started by Junus2012, 17th June 2019 18:24
    • Replies: 10
    • Views: 531
    Dominik Przyborowski
    25th June 2019, 20:06 Go to last post

  27. stretching the 0 pulse of a digital output with a certain T

    Started by iaf, 14th June 2019 14:01
    4 Attachment(s)
    • Replies: 18
    • Views: 868
    iaf
    24th June 2019, 13:50 Go to last post

  28. PCB designing and wire bonding both

    Started by ICdesignerbeginner, 24th June 2019 07:11
    • Replies: 0
    • Views: 113
    ICdesignerbeginner
    24th June 2019, 07:11 Go to last post

  29. Half Bridge driver veriloga model

    Started by michelebergo, 22nd June 2019 10:38
    • Replies: 0
    • Views: 157
    michelebergo
    22nd June 2019, 10:38 Go to last post

  30. Cadence 6.1.4 on CentOS (***** cadence)

    Started by Majid_Vatan_Parast, 21st June 2019 07:57
    1 Attachment(s)
    • Replies: 0
    • Views: 144
    Majid_Vatan_Parast
    21st June 2019, 07:57 Go to last post
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