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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 246
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 27,927
    klug
    3rd December 2007, 18:00 Go to last post

  1. DC value for VerilogA module

    Started by ashrafsazid, Today 10:31
    • Replies: 2
    • Views: 72
    dick_freebird
    Today, 16:33 Go to last post

  2. Auto Instance Name Display in Virtuoso Layout

    Started by krrao, Today 05:15
    • Replies: 1
    • Views: 58
    rangermad
    Today, 12:53 Go to last post

  3. Cadence PSS Pnoise Analysis

    Started by ashrafsazid, Yesterday 09:01
    • Replies: 7
    • Views: 175
    pancho_hideboo
    Yesterday, 15:55 Go to last post

  4. How to decide the specification of in-band phase noise of a bluetooth PLL

    Started by alex_fd, Yesterday 05:01
    • Replies: 0
    • Views: 48
    alex_fd
    Yesterday, 05:01 Go to last post

  5. Supply error detected when Run LVS

    Started by Mahmoud_Dagher, 18th July 2018 14:15
    • Replies: 1
    • Views: 84
    dick_freebird
    Yesterday, 01:08 Go to last post

  6. Gradient problems in current steering DACs

    Started by Chinmaye, 17th July 2018 17:30
    • Replies: 5
    • Views: 176
    dick_freebird
    Yesterday, 01:02 Go to last post

  7. Similar/replacement amplifier ACA0862

    Started by aminpix, 18th July 2018 21:30
    • Replies: 0
    • Views: 60
    aminpix
    18th July 2018, 21:30 Go to last post

  8. [SOLVED] Error while compiling LVS rules file

    Started by Mahmoud_Dagher, 18th July 2018 13:50
    • Replies: 0
    • Views: 44
    Mahmoud_Dagher
    18th July 2018, 14:04 Go to last post

  9. [SOLVED] What's the difference between stacked and cascode configurations?

    Started by Fávero Santos, 18th July 2018 00:12
    1 Attachment(s)
    • Replies: 1
    • Views: 109
    dick_freebird
    18th July 2018, 05:28 Go to last post

  10. [SOLVED] Calibre PEX error during generating calibre view

    Started by vieha007Electronic, 10th July 2018 00:28
    • Replies: 3
    • Views: 215
    vieha007Electronic
    16th July 2018, 18:56 Go to last post

  11. "np" layer and "pp" layer in CMOS circuit

    Started by AllenD, 12th July 2018 04:39
    1 Attachment(s)
    • Replies: 4
    • Views: 230
    AllenD
    15th July 2018, 03:55 Go to last post

  12. Fully differential Amplifier class AB

    Started by hannover90, 12th July 2018 18:24
    • Replies: 1
    • Views: 120
    erikl
    14th July 2018, 20:50 Go to last post

  13. Question about the changing of Gate terminal material

    Started by quyleanh, 13th July 2018 03:17
    • Replies: 1
    • Views: 173
    dick_freebird
    14th July 2018, 03:02 Go to last post

  14. Disable to read "cds.lib" in Ocean Run.

    Started by pancho_hideboo, 7th July 2018 06:12
    • Replies: 3
    • Views: 286
    erikl
    13th July 2018, 16:27 Go to last post

  15. Issues around ads keysight layout

    Started by adeniyiMokesioluwa, 7th July 2018 12:03
    2 Attachment(s)
    • Replies: 1
    • Views: 131
    johnjoe
    12th July 2018, 11:07 Go to last post

  16. Simples current mirror input impedance

    Started by CAMALEAO, 10th July 2018 17:16
    1 Attachment(s)
    • Replies: 7
    • Views: 253
    CAMALEAO
    12th July 2018, 10:34 Go to last post

  17. Pipeline last stage gain

    Started by shanmei, 12th July 2018 03:04
    1 Attachment(s)
    • Replies: 0
    • Views: 72
    shanmei
    12th July 2018, 03:04 Go to last post

  18. [SOLVED] How can I calculate the (W/L) ratio for nmos and pmos in below schematics?

    Started by viny9694, 9th July 2018 01:38
    2 Attachment(s)
    • Replies: 1
    • Views: 226
    dick_freebird
    10th July 2018, 19:22 Go to last post

  19. DRC Errors after No Geometry Violations

    Started by Mahmoud_Dagher, 29th June 2018 11:32
    • Replies: 9
    • Views: 274
    dick_freebird
    10th July 2018, 19:09 Go to last post

  20. How to calculate the individual widths from total width for mosfet's?

    Started by viny9694, 9th July 2018 23:55
    2 Attachment(s)
    • Replies: 1
    • Views: 78
    dick_freebird
    10th July 2018, 06:29 Go to last post

  21. Exporting from CST and Importing to ALtium

    Started by f_t, 6th July 2018 18:20
    1 Attachment(s)
    • Replies: 3
    • Views: 172
    pragash
    10th July 2018, 01:51 Go to last post

  22. [SOLVED] Help pls! n+sd to psub spacing must be <=10um error!

    Started by Enorize, 27th June 2018 00:29
    2 Attachment(s)
    • Replies: 7
    • Views: 315
    erikl
    9th July 2018, 20:08 Go to last post

  23. Verilog-a cyclically dependent error

    Started by heba_saleh, 8th July 2018 11:20
    • Replies: 3
    • Views: 160
    pancho_hideboo
    9th July 2018, 01:14 Go to last post

  24. How to do layout of a group of capacitor around 300 please?

    Started by Enorize, 27th June 2018 13:38
    • Replies: 8
    • Views: 337
    dick_freebird
    9th July 2018, 01:12 Go to last post

  25. [SOLVED] Monte Carlo Simulation in HSPICE 2008.03

    Started by rmanalo, 6th July 2018 06:07
    1 Attachment(s)
    • Replies: 3
    • Views: 215
    erikl
    7th July 2018, 23:08 Go to last post

  26. Moved: [Moved]: Verilog code to read .txt (hexa value)file and and to store in PC

    Started by vachanukb, 6th July 2018 19:41
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  27. What's the purpose the bias on the left two branches in this CMFB circuit

    Started by monglebest, 6th July 2018 17:37
    1 Attachment(s)
    • Replies: 1
    • Views: 117
    d123
    6th July 2018, 19:21 Go to last post

  28. Noise figure calculation in cadence virtuoso

    Started by pallabeebsws92, 6th July 2018 14:48
    • Replies: 0
    • Views: 82
    pallabeebsws92
    6th July 2018, 14:48 Go to last post

  29. [SOLVED] What it the Output Template for mobility, un

    Started by rmanalo, 3rd July 2018 07:59
    4 Attachment(s)
    • Replies: 3
    • Views: 160
    erikl
    5th July 2018, 22:35 Go to last post

  30. DRC metal density issue. How to fix it?

    Started by shanmei, 1st July 2018 20:11
    • Replies: 6
    • Views: 291
    rangermad
    5th July 2018, 15:08 Go to last post
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