1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    111,033
Page 1 of 630 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 18871

Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 392
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 28,060
    klug
    3rd December 2007, 18:00 Go to last post

  1. SnCx plus 07 Lead-free Silver-free alloy

    Started by neazoi, Yesterday 23:31
    1 Attachment(s)
    • Replies: 0
    • Views: 56
    neazoi
    Yesterday, 23:31 Go to last post

  2. Comparator offset measurement

    Started by assemelgohari, 25th March 2018 17:35
    2 Pages •
    1 2
    23 Attachment(s)
    • Replies: 27
    • Views: 1,749
    travelguru01
    20th September 2018, 09:05 Go to last post

  3. New technology - what to do

    Started by CAMALEAO, 5th September 2018 10:56
    • Replies: 8
    • Views: 400
    dr_kca
    18th September 2018, 07:17 Go to last post

  4. S T A R connection on the layout

    Started by CAMALEAO, 16th September 2018 19:25
    • Replies: 5
    • Views: 260
    dick_freebird
    17th September 2018, 18:25 Go to last post

  5. How to measure Chip size using SVRF for calibre DRC

    Started by sam88, 10th September 2018 19:49
    • Replies: 2
    • Views: 218
    timof
    17th September 2018, 06:55 Go to last post

  6. Extraction of level 1 parameters through simulations

    Started by hobbyiclearner, 15th September 2018 06:31
    1 Attachment(s)
    • Replies: 1
    • Views: 112
    erikl
    16th September 2018, 20:46 Go to last post

  7. Mixed IC Design Flow Using: Synopsys DC-ICC & Cadence Virtuoso

    Started by ryu_hayabusa, 17th August 2018 03:37
    • Replies: 1
    • Views: 158
    npardeepsain
    16th September 2018, 15:25 Go to last post

  8. Supply error detected when Run LVS

    Started by Mahmoud_Dagher, 18th July 2018 14:15
    • Replies: 3
    • Views: 348
    npardeepsain
    16th September 2018, 14:29 Go to last post

  9. The load seen by opamp in non-inverting config. is TWICE w.r.t. the inverting config.?

    Started by spectrallypure, 15th September 2018 16:31
    2 Attachment(s)
    • Replies: 6
    • Views: 695
    spectrallypure
    16th September 2018, 11:57 Go to last post

  10. SNR issue with continuous time 2nd order feedforward sigma delta

    Started by FAMA89, 12th September 2018 04:11
    6 Attachment(s)
    • Replies: 9
    • Views: 434
    pancho_hideboo
    16th September 2018, 07:20 Go to last post

  11. Moved: Help in tunable circuits

    Started by student14, 12th September 2018 08:14
    •  
    •  

  12. "Please check your core height setting" Error when Creating Floorplan In IC Compiler

    Started by ryu_hayabusa, 27th August 2018 18:20
    2 Attachment(s)
    • Replies: 6
    • Views: 683
    ThisIsNotSam
    14th September 2018, 19:35 Go to last post

  13. Current conveyor CCII

    Started by CAMALEAO, 12th September 2018 16:29
    2 Attachment(s)
    • Replies: 4
    • Views: 246
    BradtheRad
    14th September 2018, 02:25 Go to last post

  14. [SOLVED] TSMC n65 substrate contact for rf mos/power net layout/Latchup prevention

    Started by AllenD, 23rd August 2018 09:28
    1 Attachment(s)
    • Replies: 11
    • Views: 769
    timof
    13th September 2018, 02:54 Go to last post

  15. Auto routing constraints in cadence virtuoso

    Started by frasheed, 22nd August 2018 17:17
    • Replies: 2
    • Views: 237
    frasheed
    12th September 2018, 12:57 Go to last post

  16. How to have a research mindset in the field of analog IC design?

    Started by melkord, 12th September 2018 01:00
    • Replies: 2
    • Views: 167
    BradtheRad
    12th September 2018, 04:35 Go to last post

  17. Desat after few minutes in IR2214

    Started by rajgajera, 10th September 2018 11:47
    1 Attachment(s)
    • Replies: 2
    • Views: 145
    rajgajera
    10th September 2018, 19:25 Go to last post

  18. Jitter in fs-rms in Cadence Virtuoso/Spectre

    Started by Puppet123, 8th September 2018 07:59
    • Replies: 5
    • Views: 245
    dick_freebird
    10th September 2018, 18:39 Go to last post

  19. What's the difference in this two gain boosted structure,why results differ so much.

    Started by jktheone1987, 9th September 2018 12:40
    6 Attachment(s)
    • Replies: 3
    • Views: 218
    frankrose
    10th September 2018, 16:17 Go to last post

  20. Some gain issues on gain-boosted opa

    Started by jktheone1987, 7th September 2018 11:06
    1 Attachment(s)
    • Replies: 3
    • Views: 232
    frankrose
    9th September 2018, 13:37 Go to last post

  21. Stability of LDO (Static, Dynamic, or high freq)

    Started by MahmoudHassan, 7th September 2018 17:41
    • Replies: 3
    • Views: 237
    dick_freebird
    8th September 2018, 17:59 Go to last post

  22. Post-layout simulation of sigma-delta modulators "error"

    Started by pcca, 6th September 2018 22:01
    1 Attachment(s)
    • Replies: 0
    • Views: 135
    pcca
    6th September 2018, 22:01 Go to last post

  23. hnlCDLFormatInst errors in CDL netlist

    Started by resonance2050, 6th September 2018 16:29
    • Replies: 0
    • Views: 94
    resonance2050
    6th September 2018, 16:29 Go to last post

  24. Separating grounds in analog IC

    Started by MaryF, 5th September 2018 13:24
    • Replies: 4
    • Views: 233
    dick_freebird
    5th September 2018, 18:42 Go to last post

  25. Incomplete nets (2 sources)

    Started by MaryF, 5th September 2018 15:29
    • Replies: 1
    • Views: 145
    timof
    5th September 2018, 17:20 Go to last post

  26. EE240 Berkeley Niknejad Spring 2006

    Started by Puppet123, 5th September 2018 05:07
    • Replies: 0
    • Views: 113
    Puppet123
    5th September 2018, 05:07 Go to last post

  27. [SOLVED] low speed DAC with latch or not

    Started by shanmei, 4th September 2018 01:57
    • Replies: 3
    • Views: 252
    shanmei
    4th September 2018, 18:39 Go to last post

  28. Verilog A Code for Clocked Comparator

    Started by Puppet123, 4th September 2018 11:34
    • Replies: 1
    • Views: 208
    pancho_hideboo
    4th September 2018, 13:17 Go to last post

  29. 2nd Order Behavioral Simulation of DT Sigma Delta Modulator

    Started by Puppet123, 4th September 2018 09:37
    2 Attachment(s)
    • Replies: 1
    • Views: 138
    pancho_hideboo
    4th September 2018, 13:06 Go to last post

  30. Switched Capacitor Circuits - PSS/PAC

    Started by Puppet123, 1st September 2018 00:36
    • Replies: 12
    • Views: 625
    pancho_hideboo
    4th September 2018, 11:42 Go to last post
Powered by vBulletin™
Copyright © 2017 vBulletin Solutions, Inc. All rights reserved.