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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 3,118
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 30,688
    klug
    3rd December 2007, 18:00 Go to last post

  1. Class AB fully differential amplifier design issue

    Started by Junus2012, Yesterday 17:13
    1 Attachment(s)
    • Replies: 2
    • Views: 131
    FvM
    Yesterday, 22:42 Go to last post

  2. Fully-Differential folded cascode amplifier with enhanced gain

    Started by Junus2012, 7th November 2019 12:29
    3 Attachment(s)
    • Replies: 10
    • Views: 473
    sutapanaki
    Yesterday, 19:04 Go to last post

  3. Tapered Buffer Peak Voltages

    Started by littlerock, 11th November 2019 11:41
    2 Attachment(s)
    • Replies: 0
    • Views: 135
    littlerock
    11th November 2019, 11:41 Go to last post

  4. Moved: [SOLVED] inverter output Vhigh voltage

    Started by AllenD, 11th November 2019 17:43
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  5. DAC unit cap selection for SAR ADC

    Started by spswaroopa, 6th November 2019 12:20
    • Replies: 3
    • Views: 208
    timof
    9th November 2019, 02:38 Go to last post

  6. Resistor mismatch hand calculation and simulation

    Started by ashrafsazid, 5th November 2019 23:50
    1 Attachment(s)
    • Replies: 4
    • Views: 248
    wwfeldman
    7th November 2019, 17:14 Go to last post

  7. Rail to rail input folded operational amplifier

    Started by Junus2012, 7th November 2019 15:07
    1 Attachment(s)
    • Replies: 0
    • Views: 143
    Junus2012
    7th November 2019, 15:07 Go to last post

  8. Feasibility Analyses in Cadence

    Started by Junus2012, 7th November 2019 10:03
    • Replies: 0
    • Views: 119
    Junus2012
    7th November 2019, 10:03 Go to last post

  9. How to connect N_BPW_33RF switch in RF NMOS characterization in UMC 130nm process

    Started by anas171, 6th November 2019 04:26
    1 Attachment(s)
    • Replies: 1
    • Views: 110
    deep_sea
    6th November 2019, 11:05 Go to last post

  10. Capacitive Boost or Charge-Pump DC-DC Converter

    Started by WASDQWERTY, 23rd October 2019 11:08
    4 Attachment(s)
    • Replies: 8
    • Views: 528
    BradtheRad
    6th November 2019, 08:29 Go to last post

  11. Difference between NMOS/PMOS with and without Deep Nwell

    Started by hafis.m, 25th October 2019 09:52
    • Replies: 2
    • Views: 231
    dick_freebird
    6th November 2019, 02:55 Go to last post

  12. Analog Layout - Sharing source/drain

    Started by big_fudge98, 2nd November 2019 18:48
    • Replies: 1
    • Views: 216
    frankrose
    5th November 2019, 19:42 Go to last post

  13. Source follower design issue for cascoded two stage op-amp

    Started by Junus2012, 5th November 2019 16:26
    1 Attachment(s)
    • Replies: 0
    • Views: 113
    Junus2012
    5th November 2019, 16:26 Go to last post

  14. What does the NP stand for in SSGNP and FFGNP

    Started by janthonym, 4th November 2019 18:44
    • Replies: 0
    • Views: 122
    janthonym
    4th November 2019, 18:44 Go to last post

  15. While checking LVS I got following error LOGS

    Started by MubarakKhan, 4th November 2019 10:57
    • Replies: 0
    • Views: 151
    MubarakKhan
    4th November 2019, 10:57 Go to last post

  16. Modelling power supply for cadence simulations

    Started by big_fudge98, 3rd November 2019 13:16
    • Replies: 4
    • Views: 251
    frankrose
    3rd November 2019, 21:43 Go to last post

  17. RHP zero cancellation in miller compensated opamp

    Started by big_fudge98, 3rd November 2019 10:45
    • Replies: 2
    • Views: 192
    FvM
    3rd November 2019, 13:09 Go to last post

  18. MOSFET soi, to use LTSpice

    Started by lufer17, 2nd November 2019 15:27
    • Replies: 1
    • Views: 188
    dick_freebird
    2nd November 2019, 20:34 Go to last post

  19. Noise calculation in static-dynamic circuit

    Started by amr.maghraby, 31st October 2019 09:44
    • Replies: 3
    • Views: 212
    pancho_hideboo
    2nd November 2019, 19:15 Go to last post

  20. Relxpert model file which supports UMC65 for reliability simulation

    Started by abhishek260, 1st November 2019 09:19
    • Replies: 1
    • Views: 202
    ThisIsNotSam
    1st November 2019, 10:27 Go to last post

  21. Running different type of simulation in one environment

    Started by Junus2012, 30th October 2019 14:51
    1 Attachment(s)
    • Replies: 6
    • Views: 355
    pancho_hideboo
    1st November 2019, 01:21 Go to last post

  22. TSMC65nm CRN65LP PDK Calibre and PEX Issues

    Started by Puppet123, 31st October 2019 12:19
    • Replies: 1
    • Views: 146
    timof
    31st October 2019, 17:33 Go to last post

  23. [SOLVED] ASIC Standar Cell Library

    Started by hungquoc, 31st October 2019 17:11
    • Replies: 1
    • Views: 134
    FvM
    31st October 2019, 17:32 Go to last post

  24. Physical Verification with TSMC65nm CRN65LP PDK

    Started by Puppet123, 18th September 2019 04:14
    • Replies: 2
    • Views: 319
    Puppet123
    31st October 2019, 11:25 Go to last post

  25. VIH, VIL in worst, best and typical case discussion

    Started by tigerajs, 29th October 2019 03:20
    1 Attachment(s)
    • Replies: 1
    • Views: 196
    chendong1017
    31st October 2019, 03:27 Go to last post

  26. [SOLVED] Making a mathematical expression between two parameters in ADE GXL output setup windo

    Started by Junus2012, 30th October 2019 13:06
    1 Attachment(s)
    • Replies: 5
    • Views: 284
    Junus2012
    30th October 2019, 14:50 Go to last post

  27. Difference between input and output offset voltage

    Started by Junus2012, 28th October 2019 12:26
    • Replies: 7
    • Views: 324
    asdf44
    30th October 2019, 13:54 Go to last post

  28. Is it possible to compensate the VOS by adjusting the common mode outout voltage VCM?

    Started by Junus2012, 28th October 2019 11:12
    4 Attachment(s)
    • Replies: 15
    • Views: 701
    Junus2012
    30th October 2019, 11:10 Go to last post

  29. WPE in a dual gate oxide (DGO) 90um process (4 pockets).

    Started by sr_orion, 29th October 2019 13:57
    1 Attachment(s)
    • Replies: 0
    • Views: 136
    sr_orion
    29th October 2019, 13:57 Go to last post

  30. What things we need to take care a lenghty routing let's say 5000um

    Started by saran826, 6th October 2019 06:24
    • Replies: 3
    • Views: 514
    dick_freebird
    27th October 2019, 19:57 Go to last post
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