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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 6,922
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 34,511
    klug
    3rd December 2007, 18:00 Go to last post

  1. Rail to rail circuit simulation

    Started by ibiteee, 19th May 2020 15:35
    2 Attachment(s)
    • Replies: 8
    • Views: 321
    t4_v
    Today, 09:09 Go to last post

  2. Time Interleaved ADC Filtering at Output

    Started by Puppet123, 23rd May 2020 22:40
    • Replies: 3
    • Views: 254
    sutapanaki
    Yesterday, 23:13 Go to last post

  3. Need for safe phase margin when dealing with sin input signals

    Started by Junus2012, 22nd May 2020 22:04
    2 Attachment(s)
    • Replies: 8
    • Views: 278
    danadakk
    23rd May 2020, 21:47 Go to last post

  4. Bulk fixing (gluing) CMOS

    Started by lufer17, 23rd May 2020 14:49
    1 Attachment(s)
    • Replies: 1
    • Views: 134
    dick_freebird
    23rd May 2020, 18:46 Go to last post

  5. Verilog and VHDL noise modelling

    Started by deep_sea, 20th May 2020 12:28
    • Replies: 5
    • Views: 290
    ThisIsNotSam
    22nd May 2020, 11:14 Go to last post

  6. What are the typical lab characterization equipment used for testing Analog ICs?

    Started by doncarlosalbatros, 21st May 2020 01:20
    • Replies: 3
    • Views: 311
    t4_v
    21st May 2020, 09:07 Go to last post

  7. The stability of the power amplifier

    Started by OZZAA, 5th April 2020 08:01
    4 Attachment(s)
    • Replies: 3
    • Views: 500
    BigBoss
    20th May 2020, 01:01 Go to last post

  8. sizing of floating current sources in folded cascode amplifier ?

    Started by cmos_ajay, 18th May 2020 10:30
    2 Attachment(s)
    • Replies: 3
    • Views: 266
    t4_v
    19th May 2020, 10:13 Go to last post

  9. Simulating AC performance of the amplifier with switched capacitor circuit

    Started by Junus2012, 13th May 2020 23:40
    • Replies: 11
    • Views: 745
    LvW
    16th May 2020, 09:07 Go to last post

  10. Trends in Analog IP for ASIC Design

    Started by JElectric, 6th May 2020 12:46
    • Replies: 7
    • Views: 649
    Puppet123
    15th May 2020, 23:44 Go to last post

  11. Layout of big transistors

    Started by Junus2012, 14th May 2020 23:19
    • Replies: 3
    • Views: 299
    dick_freebird
    15th May 2020, 18:31 Go to last post

  12. Implementation of Operational Transconductance Amplifier in LTSpice

    Started by robi10101298, 7th May 2020 21:35
    5 Attachment(s)
    • Replies: 12
    • Views: 865
    t4_v
    15th May 2020, 10:52 Go to last post

  13. Biasing the amplifier with high current mirror ration

    Started by Junus2012, 10th May 2020 00:35
    2 Attachment(s)
    • Replies: 11
    • Views: 728
    Junus2012
    14th May 2020, 23:40 Go to last post

  14. [HSpice] Question about HSpice Simulation of Similar SRAM Column/Network

    Started by EEPuppyPuppy, 14th May 2020 05:06
    • Replies: 0
    • Views: 234
    EEPuppyPuppy
    14th May 2020, 05:06 Go to last post

  15. Matching the biasing circuit to the core amplifier

    Started by Junus2012, 2nd May 2020 22:07
    2 Pages •
    1 2
    8 Attachment(s)
    • Replies: 20
    • Views: 1,847
    Junus2012
    13th May 2020, 17:39 Go to last post

  16. Leakage currents in nano meter scale CMOS processes

    Started by hobbyiclearner, 5th May 2020 12:23
    • Replies: 7
    • Views: 1,563
    t4_v
    13th May 2020, 10:39 Go to last post

  17. SAR ADC Architecture Blocks

    Started by Adithya_Pai, 1st May 2020 19:40
    3 Attachment(s)
    • Replies: 5
    • Views: 1,227
    sutapanaki
    9th May 2020, 18:46 Go to last post

  18. Is this CMRR plot correct?

    Started by fat_123, 7th May 2020 21:19
    1 Attachment(s)
    • Replies: 3
    • Views: 399
    stenzer
    9th May 2020, 13:32 Go to last post

  19. Difference between Sample/Value Function in Cadence Spectre

    Started by Puppet123, 1st May 2020 05:18
    • Replies: 10
    • Views: 1,375
    vivekroy
    9th May 2020, 12:05 Go to last post

  20. CMOS differential OPAmp

    Started by MILIND_7, 18th March 2020 10:53
    • Replies: 5
    • Views: 671
    vivekroy
    9th May 2020, 10:13 Go to last post

  21. Level converter devices

    Started by joniengr, 8th May 2020 08:24
    • Replies: 1
    • Views: 188
    KlausST
    8th May 2020, 08:52 Go to last post

  22. Cascoding the two stage folded class AB ampliifer

    Started by Junus2012, 28th March 2020 17:31
    2 Pages •
    1 2
    11 Attachment(s)
    • Replies: 21
    • Views: 3,307
    Junus2012
    7th May 2020, 21:59 Go to last post

  23. Measure inl of an ADC in cadence

    Started by Chinmaye, 17th February 2020 05:25
    • Replies: 5
    • Views: 756
    Puppet123
    7th May 2020, 21:21 Go to last post

  24. Relationship between settling accuracy and resolution

    Started by Junus2012, 3rd May 2020 16:17
    • Replies: 3
    • Views: 953
    Puppet123
    7th May 2020, 21:12 Go to last post

  25. Simulating Gain/PM of Constant GM Current Reference in Cadence

    Started by urawizard, 24th April 2020 07:18
    1 Attachment(s)
    • Replies: 12
    • Views: 831
    vivekroy
    7th May 2020, 16:21 Go to last post

  26. Gain peaks of per-stage in multistage mmic PA design

    Started by maxsidou, 4th May 2020 09:25
    2 Attachment(s)
    • Replies: 2
    • Views: 882
    maxsidou
    7th May 2020, 15:44 Go to last post

  27. OSC phase noise modeling, veriloga model generation, and verification

    Started by newmedi, 7th May 2020 15:32
    • Replies: 0
    • Views: 132
    newmedi
    7th May 2020, 15:32 Go to last post

  28. Settling time of opam at different closed loop gain

    Started by Junus2012, 3rd May 2020 16:13
    • Replies: 7
    • Views: 1,123
    sutapanaki
    6th May 2020, 19:13 Go to last post

  29. How to approach CDAC of SAR using SPICE

    Started by Adithya_Pai, 6th May 2020 16:34
    • Replies: 0
    • Views: 196
    Adithya_Pai
    6th May 2020, 16:34 Go to last post

  30. Stability circles smith chart problem

    Started by yefj, 26th April 2020 19:06
    2 Attachment(s)
    • Replies: 1
    • Views: 305
    OrangeHalo
    6th May 2020, 03:14 Go to last post
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