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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 2,672
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 30,215
    klug
    3rd December 2007, 18:00 Go to last post

  1. deviding Y value by X values in Cadence Virtuoso calculator

    Started by Junus2012, Today 16:29
    2 Attachment(s)
    • Replies: 5
    • Views: 74
    pancho_hideboo
    Today, 19:00 Go to last post

  2. Operational amplifier driving capability test

    Started by Junus2012, Today 16:00
    • Replies: 4
    • Views: 57
    Junus2012
    Today, 17:12 Go to last post

  3. Converting verilog code into a symbol during AMS simulation

    Started by Chinmaye, Today 08:40
    • Replies: 3
    • Views: 60
    pancho_hideboo
    Today, 15:37 Go to last post

  4. Differential and common mode input resistance of the fully diffferential amplifier

    Started by Junus2012, 2nd September 2019 13:17
    2 Pages •
    1 2
    8 Attachment(s)
    • Replies: 22
    • Views: 859
    Junus2012
    Today, 09:55 Go to last post

  5. Level Shifters: Trends in Delay and Transition Time

    Started by janthonym, Yesterday 23:22
    • Replies: 1
    • Views: 111
    BradtheRad
    Today, 08:21 Go to last post

  6. What is the difference between LVS and ERC ?

    Started by MubarakKhan, 13th September 2019 11:36
    • Replies: 2
    • Views: 160
    timof
    Today, 03:55 Go to last post

  7. Analog 16:1 MUX IC question, 4 vs 1 stage, transmission gate vs nmos

    Started by OG_, Yesterday 18:06
    2 Attachment(s)
    • Replies: 1
    • Views: 90
    dick_freebird
    Today, 02:05 Go to last post

  8. [SOLVED] AMS simulation of D-FF

    Started by Chinmaye, Yesterday 12:30
    1 Attachment(s)
    • Replies: 2
    • Views: 125
    dick_freebird
    Yesterday, 18:19 Go to last post

  9. ConnectLib files in ams simulation Cadence

    Started by Chinmaye, 15th September 2019 19:19
    • Replies: 0
    • Views: 101
    Chinmaye
    15th September 2019, 19:19 Go to last post

  10. Combine circuit and Verilog in Cadence

    Started by Chinmaye, 14th September 2019 18:09
    • Replies: 1
    • Views: 186
    Dominik Przyborowski
    14th September 2019, 18:30 Go to last post

  11. Problems in Verifying Silterra Library Cells using Calibre

    Started by JLHW, 13th September 2019 17:12
    1 Attachment(s)
    • Replies: 0
    • Views: 91
    JLHW
    13th September 2019, 17:12 Go to last post

  12. Verilog-a code to latch analog voltages

    Started by Chinmaye, 11th September 2019 07:11
    1 Attachment(s)
    • Replies: 7
    • Views: 292
    vivekroy
    12th September 2019, 19:51 Go to last post

  13. DNL/INL Measurement in Cadence for DAC

    Started by Puppet123, 12th September 2019 01:45
    • Replies: 2
    • Views: 214
    Dominik Przyborowski
    12th September 2019, 04:44 Go to last post

  14. INL/DNL Measurement from Cadence Spectre/Virtuoso Output

    Started by Puppet123, 6th September 2019 21:44
    • Replies: 7
    • Views: 422
    pancho_hideboo
    12th September 2019, 01:32 Go to last post

  15. Verilog-a code for differential amplifier

    Started by Chinmaye, 11th September 2019 07:20
    • Replies: 4
    • Views: 201
    Chinmaye
    11th September 2019, 18:49 Go to last post

  16. Current reference design for CS-DAC

    Started by Shishira, 6th September 2019 19:07
    1 Attachment(s)
    • Replies: 5
    • Views: 312
    Dominik Przyborowski
    11th September 2019, 06:07 Go to last post

  17. How to change the m factor (multiplication factor) for Instances in cadence

    Started by Junus2012, 26th August 2019 19:31
    1 Attachment(s)
    • Replies: 5
    • Views: 278
    Dominik Przyborowski
    10th September 2019, 20:12 Go to last post

  18. Charge pump topology

    Started by bharath_k, 5th September 2019 11:44
    2 Attachment(s)
    • Replies: 4
    • Views: 558
    bharath_k
    9th September 2019, 09:42 Go to last post

  19. ADE-XL: 2 tests have a same variable but it is constant for test1 and swept for tes2

    Started by circuitking, 9th September 2019 01:56
    • Replies: 1
    • Views: 175
    Dominik Przyborowski
    9th September 2019, 04:46 Go to last post

  20. W/L of pMOS and nMOS of CD4007 Chip.

    Started by vijender13, 6th September 2019 06:20
    • Replies: 3
    • Views: 231
    frankrose
    8th September 2019, 22:24 Go to last post

  21. Generate pulses of different widths

    Started by Chinmaye, 8th September 2019 10:20
    • Replies: 1
    • Views: 145
    erikl
    8th September 2019, 20:21 Go to last post

  22. Error and Questions related to Calibre 2015 in Cadence

    Started by JLHW, 8th September 2019 18:22
    2 Attachment(s)
    • Replies: 0
    • Views: 134
    JLHW
    8th September 2019, 18:22 Go to last post

  23. Changing the 'VSS' value in CppSim

    Started by vivekroy, 8th September 2019 14:04
    • Replies: 0
    • Views: 132
    vivekroy
    8th September 2019, 14:04 Go to last post

  24. Help on Ocean scripting: run one analysis and use that results in another

    Started by circuitking, 6th September 2019 21:59
    • Replies: 8
    • Views: 383
    vivekroy
    8th September 2019, 13:37 Go to last post

  25. Factors deciding Silicon Wafer Thickness

    Started by Vishu21_95, 29th August 2019 06:53
    • Replies: 2
    • Views: 231
    dick_freebird
    5th September 2019, 02:22 Go to last post

  26. Interdigitation techniques when working with FinFETs

    Started by mamir, 4th September 2019 20:59
    • Replies: 0
    • Views: 139
    mamir
    4th September 2019, 20:59 Go to last post

  27. Deaign of low ON resistor CMOS transmission gate

    Started by Junus2012, 17th April 2019 12:26
    1 Attachment(s)
    • Replies: 18
    • Views: 4,141
    dick_freebird
    4th September 2019, 04:18 Go to last post

  28. LVS Subtype error at layout

    Started by rty94, 28th August 2019 22:23
    • Replies: 2
    • Views: 306
    k_90
    3rd September 2019, 16:00 Go to last post

  29. Inverters as Level Shifter with HVT and LVT transistors

    Started by john.zhang, 3rd September 2019 04:37
    • Replies: 3
    • Views: 386
    vivekroy
    3rd September 2019, 10:39 Go to last post

  30. How to differentiate offset voltage error from CMRR and PSRR

    Started by Junus2012, 2nd September 2019 17:16
    1 Attachment(s)
    • Replies: 4
    • Views: 202
    Junus2012
    3rd September 2019, 10:23 Go to last post
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