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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 1,942
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 29,482
    klug
    3rd December 2007, 18:00 Go to last post

  1. CMRR is less than the DC differential gain

    Started by Junus2012, Yesterday 18:24
    • Replies: 6
    • Views: 86
    FvM
    Today, 06:46 Go to last post

  2. "calibre view generation encountered a fatal error" but spectre PEX extraction works

    Started by OG_, 11th June 2019 15:48
    4 Attachment(s)
    • Replies: 11
    • Views: 498
    ljp2706
    Today, 01:25 Go to last post

  3. stretching the 0 pulse of a digital output with a certain T

    Started by iaf, 14th June 2019 14:01
    1 Attachment(s)
    • Replies: 5
    • Views: 191
    Aussie Susan
    Yesterday, 23:59 Go to last post

  4. [SOLVED] measuring the parasitic capacitance at a certain node in cadence

    Started by amr.maghraby, Yesterday 14:23
    • Replies: 7
    • Views: 103
    ThisIsNotSam
    Yesterday, 20:47 Go to last post

  5. Mismatch Contribution Analysis

    Started by rosaeidi, Yesterday 17:26
    • Replies: 1
    • Views: 46
    frankrose
    Yesterday, 18:43 Go to last post

  6. LC VCO with Capacitor filter, what is the cap doing?

    Started by mvj, Yesterday 11:37
    1 Attachment(s)
    • Replies: 1
    • Views: 83
    BigBoss
    Yesterday, 18:28 Go to last post

  7. PMOS WELL of same bulk potential of different transistor groups

    Started by Junus2012, 11th June 2019 17:41
    • Replies: 5
    • Views: 229
    sutapanaki
    13th June 2019, 00:37 Go to last post

  8. layout connection using different metalization layers

    Started by Junus2012, 11th June 2019 14:10
    • Replies: 7
    • Views: 169
    Junus2012
    12th June 2019, 23:03 Go to last post

  9. Port size in layout design

    Started by Junus2012, 11th June 2019 16:00
    • Replies: 4
    • Views: 143
    Junus2012
    12th June 2019, 23:01 Go to last post

  10. current mirror matching issue

    Started by Junus2012, 9th June 2019 18:55
    1 Attachment(s)
    • Replies: 7
    • Views: 242
    Junus2012
    12th June 2019, 22:49 Go to last post

  11. gate connection using poly vs metal

    Started by Junus2012, 9th June 2019 19:19
    1 Attachment(s)
    • Replies: 5
    • Views: 251
    dick_freebird
    11th June 2019, 23:15 Go to last post

  12. Drai and source via contact

    Started by Junus2012, 11th June 2019 14:01
    • Replies: 1
    • Views: 92
    Dominik Przyborowski
    11th June 2019, 20:40 Go to last post

  13. guard ring contacts for the PMOS transistors

    Started by Junus2012, 11th June 2019 13:59
    • Replies: 1
    • Views: 78
    ljp2706
    11th June 2019, 16:17 Go to last post

  14. Layout Abutment Sitting in the TSMC PDK

    Started by JAVAD_B, 11th June 2019 09:46
    1 Attachment(s)
    • Replies: 3
    • Views: 131
    ljp2706
    11th June 2019, 16:11 Go to last post

  15. TSMC 65nm Inductor Finder Parameters

    Started by mahir, 10th June 2019 15:21
    • Replies: 2
    • Views: 88
    mahir
    11th June 2019, 08:25 Go to last post

  16. Run Veriloga demo in hspice 2013.03-SP2 error

    Started by yyy963741tw, 11th June 2019 08:19
    2 Attachment(s)
    • Replies: 0
    • Views: 81
    yyy963741tw
    11th June 2019, 08:19 Go to last post

  17. [SOLVED] How to calculate the input-refered noise for two OTA in parallel?

    Started by nidare, 9th June 2019 16:43
    • Replies: 4
    • Views: 240
    nidare
    10th June 2019, 11:41 Go to last post

  18. Plotting waveform in Mathlab from Cadence

    Started by Junus2012, 15th May 2019 22:11
    • Replies: 5
    • Views: 1,001
    ljp2706
    9th June 2019, 22:04 Go to last post

  19. Pin definition in TSMC 0.18um

    Started by JAVAD_B, 7th June 2019 14:15
    • Replies: 4
    • Views: 238
    JAVAD_B
    9th June 2019, 07:46 Go to last post

  20. devideing large MOSFET gate using muti fingers

    Started by Junus2012, 7th June 2019 18:05
    • Replies: 4
    • Views: 183
    Dominik Przyborowski
    8th June 2019, 23:39 Go to last post

  21. When was Cadence Maestro introduced into Cadence Virtuoso ?

    Started by Puppet123, 11th December 2018 05:31
    • Replies: 2
    • Views: 482
    pancho_hideboo
    8th June 2019, 19:19 Go to last post

  22. decoupling capacitors in integrated circuit design

    Started by Junus2012, 5th June 2019 20:37
    • Replies: 4
    • Views: 252
    ljp2706
    7th June 2019, 20:17 Go to last post

  23. Input transconductance relationship ti the differential or common mode voltage

    Started by Junus2012, 3rd June 2019 20:13
    • Replies: 7
    • Views: 459
    Junus2012
    7th June 2019, 17:56 Go to last post

  24. Hot NWELL warning in layout design

    Started by Junus2012, 30th May 2019 13:48
    • Replies: 6
    • Views: 347
    Junus2012
    7th June 2019, 17:54 Go to last post

  25. Aspect ratio of the matched transistor array

    Started by Junus2012, 27th May 2019 16:42
    • Replies: 4
    • Views: 348
    ljp2706
    6th June 2019, 01:53 Go to last post

  26. Programming the LTC6904

    Started by lerameur, 5th June 2019 21:32
    • Replies: 4
    • Views: 163
    lerameur
    5th June 2019, 23:33 Go to last post

  27. Layout design issue of a multi branches current mirror

    Started by Junus2012, 5th June 2019 18:08
    1 Attachment(s)
    • Replies: 2
    • Views: 189
    Junus2012
    5th June 2019, 20:14 Go to last post

  28. Op-amp and compensation

    Started by venn_ng, 3rd June 2019 03:22
    1 Attachment(s)
    • Replies: 3
    • Views: 219
    sutapanaki
    3rd June 2019, 20:00 Go to last post

  29. Parasitic capacitor extraction: huge value

    Started by Anomis, 30th May 2019 10:08
    2 Attachment(s)
    • Replies: 6
    • Views: 319
    sutapanaki
    3rd June 2019, 17:35 Go to last post

  30. “curve-fit based” method for III-V devices

    Started by senmeis, 3rd June 2019 14:08
    • Replies: 0
    • Views: 65
    senmeis
    3rd June 2019, 14:08 Go to last post
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