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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 181
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 27,853
    klug
    3rd December 2007, 18:00 Go to last post

  1. Plot lambda vs length in Cadence

    Started by bharath_k, Yesterday 19:20
    1 Attachment(s)
    • Replies: 4
    • Views: 103
    rmanalo
    Today, 08:44 Go to last post

  2. Folded cascode OTA design

    Started by Shishira, 18th June 2018 11:31
    1 Attachment(s)
    • Replies: 11
    • Views: 346
    Dominik Przyborowski
    Yesterday, 16:21 Go to last post

  3. Technology Constants Estimation

    Started by rmanalo, Yesterday 13:14
    1 Attachment(s)
    • Replies: 0
    • Views: 83
    rmanalo
    Yesterday, 13:14 Go to last post

  4. Common Mode Feedback Test Circuit

    Started by Majid_Vatan_Parast, 21st June 2018 13:31
    1 Attachment(s)
    • Replies: 2
    • Views: 116
    Majid_Vatan_Parast
    Yesterday, 08:18 Go to last post

  5. How to get selected points in a path

    Started by vinodh saminathan, 21st June 2018 06:35
    • Replies: 1
    • Views: 59
    KlausST
    21st June 2018, 07:09 Go to last post

  6. [SOLVED] LVS problem when adding a DNW to HV NMOS in TSMC 65nm

    Started by aletar, 19th June 2018 16:03
    1 Attachment(s)
    • Replies: 3
    • Views: 104
    aletar
    20th June 2018, 15:12 Go to last post

  7. extract the dc current

    Started by shanmei, 20th June 2018 01:10
    • Replies: 4
    • Views: 123
    smijesh
    20th June 2018, 06:54 Go to last post

  8. Floating Stimuli in ADE/ADEXL

    Started by ljp2706, 19th June 2018 18:25
    • Replies: 2
    • Views: 72
    ljp2706
    20th June 2018, 03:37 Go to last post

  9. [HSpice] Invertor Simulation Problem

    Started by EEPuppyPuppy, 17th June 2018 22:37
    1 Attachment(s)
    • Replies: 2
    • Views: 147
    EEPuppyPuppy
    18th June 2018, 01:44 Go to last post

  10. [SOLVED] [HSpice] Definition of model/subckt ... is not found for the element ...

    Started by EEPuppyPuppy, 17th June 2018 11:31
    1 Attachment(s)
    • Replies: 0
    • Views: 95
    EEPuppyPuppy
    17th June 2018, 11:31 Go to last post

  11. [SOLVED] HSpice error: missing library entry name

    Started by EEPuppyPuppy, 14th June 2018 18:26
    • Replies: 4
    • Views: 206
    EEPuppyPuppy
    17th June 2018, 11:20 Go to last post

  12. Moved: [HSpice] Definition of model/subckt ... is not found for the element ...

    Started by EEPuppyPuppy, 17th June 2018 11:26
    •  
    •  

  13. Spice model to VLSI

    Started by clros, 15th June 2018 12:08
    • Replies: 4
    • Views: 189
    jjx
    16th June 2018, 12:55 Go to last post

  14. NMOS and PMOS W/L Ratio

    Started by hetang0503, 14th June 2018 12:30
    • Replies: 2
    • Views: 152
    frankrose
    16th June 2018, 01:10 Go to last post

  15. [moved] Conventional well device and flipped well device

    Started by revoorsandeep, 4th June 2018 16:43
    1 Attachment(s)
    • Replies: 5
    • Views: 391
    erikl
    15th June 2018, 23:21 Go to last post

  16. CMOS current reference with beta multiplier and inverse widlar current source

    Started by deveshkm, 14th April 2018 18:29
    1 Attachment(s)
    • Replies: 1
    • Views: 375
    nitishn5
    15th June 2018, 08:00 Go to last post

  17. MAGIC real technology files

    Started by okguy, 14th June 2018 20:11
    • Replies: 2
    • Views: 162
    dick_freebird
    15th June 2018, 02:21 Go to last post

  18. Why the Poly gate layer is longer than Select layer in PCell?

    Started by quyleanh, 1st June 2018 08:07
    1 Attachment(s)
    • Replies: 8
    • Views: 400
    quyleanh
    14th June 2018, 03:07 Go to last post

  19. ADS Layout to Cadence Layout

    Started by Puppet123, 13th June 2018 15:00
    • Replies: 0
    • Views: 96
    Puppet123
    13th June 2018, 15:00 Go to last post

  20. [SOLVED] Import a cell library into cadence virtuoso

    Started by Mahmoud_Dagher, 12th June 2018 17:42
    • Replies: 1
    • Views: 87
    dick_freebird
    12th June 2018, 18:20 Go to last post

  21. How can I Draw Layout of CNTFET.

    Started by MUKESHBEG, 12th June 2018 17:04
    • Replies: 0
    • Views: 69
    MUKESHBEG
    12th June 2018, 17:04 Go to last post

  22. [SOLVED] Bondpad and Chip Guardring connection GF BiCMOS 130nm

    Started by adancy24, 11th June 2018 13:33
    • Replies: 2
    • Views: 132
    adancy24
    11th June 2018, 15:36 Go to last post

  23. Multilayer inductor parameter measurement with VNA

    Started by Martynas JankÅ«nas, 3rd May 2018 20:48
    3 Attachment(s)
    • Replies: 5
    • Views: 399
    volker@muehlhaus
    11th June 2018, 08:25 Go to last post

  24. In chip integrated decoupling capacitors

    Started by strabush, 10th June 2018 14:26
    • Replies: 2
    • Views: 191
    dick_freebird
    11th June 2018, 03:53 Go to last post

  25. How to simulate Cgg, Cgs, Cgd vs. Vgs by HSPICE with BSIM-CMG and ptm modelcard?

    Started by et308191, 9th June 2018 08:31
    • Replies: 0
    • Views: 317
    et308191
    9th June 2018, 08:31 Go to last post

  26. Common Mode Feedback

    Started by Majid_Vatan_Parast, 6th June 2018 15:12
    6 Attachment(s)
    • Replies: 12
    • Views: 495
    Majid_Vatan_Parast
    7th June 2018, 15:34 Go to last post

  27. Open loop gain and phase plotting in a closed loop system

    Started by CAMALEAO, 31st May 2018 15:04
    • Replies: 5
    • Views: 321
    LvW
    6th June 2018, 10:45 Go to last post

  28. Binary weighted switch for r-2r DAC

    Started by mburakbaran, 1st June 2018 12:16
    2 Attachment(s)
    • Replies: 12
    • Views: 556
    frankrose
    4th June 2018, 17:29 Go to last post

  29. How to decide the pin pitch distance in physical layout designing?

    Started by isky, 3rd June 2018 15:18
    2 Attachment(s)
    • Replies: 2
    • Views: 199
    rangermad
    4th June 2018, 12:57 Go to last post

  30. TSMC 65nm Substrate Issues

    Started by Puppet123, 2nd June 2018 22:05
    • Replies: 1
    • Views: 171
    quyleanh
    4th June 2018, 03:46 Go to last post
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