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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 1,980
    1st May 2018, 14:19 Go to last post
  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 29,521
    3rd December 2007, 18:00 Go to last post
    • Replies: 18
    • Views: 482
    Today, 13:50 Go to last post
  1. Half Bridge driver veriloga model

    Started by michelebergo, 22nd June 2019 10:38
    • Replies: 0
    • Views: 92
    22nd June 2019, 10:38 Go to last post
    • Replies: 0
    • Views: 83
    21st June 2019, 07:57 Go to last post
  2. Analog Layout - Multipliers and Fingers

    Started by Puppet123, 21st June 2019 02:40
    • Replies: 1
    • Views: 93
    21st June 2019, 03:02 Go to last post
  3. Opamp Layout Example

    Started by Puppet123, 19th June 2019 18:05
    • Replies: 1
    • Views: 144
    20th June 2019, 05:32 Go to last post
  4. CMRR is less than the DC differential gain

    Started by Junus2012, 17th June 2019 18:24
    • Replies: 8
    • Views: 212
    19th June 2019, 18:29 Go to last post
  5. TSMC 65nm mocap_rf varactor

    Started by mahir, 18th June 2019 15:02
    • Replies: 1
    • Views: 140
    18th June 2019, 23:27 Go to last post
  6. LC VCO with Capacitor filter, what is the cap doing?

    Started by mvj, 17th June 2019 11:37
    • Replies: 2
    • Views: 163
    18th June 2019, 14:31 Go to last post
    • Replies: 7
    • Views: 210
    17th June 2019, 20:47 Go to last post
  7. Mismatch Contribution Analysis

    Started by rosaeidi, 17th June 2019 17:26
    • Replies: 1
    • Views: 98
    17th June 2019, 18:43 Go to last post
    • Replies: 5
    • Views: 287
    13th June 2019, 00:37 Go to last post
    • Replies: 7
    • Views: 240
    12th June 2019, 23:03 Go to last post
  8. Port size in layout design

    Started by Junus2012, 11th June 2019 16:00
    • Replies: 4
    • Views: 189
    12th June 2019, 23:01 Go to last post
  9. current mirror matching issue

    Started by Junus2012, 9th June 2019 18:55
    • Replies: 7
    • Views: 316
    12th June 2019, 22:49 Go to last post
  10. gate connection using poly vs metal

    Started by Junus2012, 9th June 2019 19:19
    • Replies: 5
    • Views: 314
    11th June 2019, 23:15 Go to last post
  11. Drai and source via contact

    Started by Junus2012, 11th June 2019 14:01
    • Replies: 1
    • Views: 115
    11th June 2019, 20:40 Go to last post
  12. guard ring contacts for the PMOS transistors

    Started by Junus2012, 11th June 2019 13:59
    • Replies: 1
    • Views: 102
    11th June 2019, 16:17 Go to last post
  13. Layout Abutment Sitting in the TSMC PDK

    Started by JAVAD_B, 11th June 2019 09:46
    • Replies: 3
    • Views: 170
    11th June 2019, 16:11 Go to last post
  14. TSMC 65nm Inductor Finder Parameters

    Started by mahir, 10th June 2019 15:21
    • Replies: 2
    • Views: 128
    11th June 2019, 08:25 Go to last post
  15. Run Veriloga demo in hspice 2013.03-SP2 error

    Started by yyy963741tw, 11th June 2019 08:19
    • Replies: 0
    • Views: 101
    11th June 2019, 08:19 Go to last post
    • Replies: 4
    • Views: 283
    10th June 2019, 11:41 Go to last post
  16. Plotting waveform in Mathlab from Cadence

    Started by Junus2012, 15th May 2019 22:11
    • Replies: 5
    • Views: 1,041
    9th June 2019, 22:04 Go to last post
  17. Pin definition in TSMC 0.18um

    Started by JAVAD_B, 7th June 2019 14:15
    • Replies: 4
    • Views: 296
    9th June 2019, 07:46 Go to last post
  18. devideing large MOSFET gate using muti fingers

    Started by Junus2012, 7th June 2019 18:05
    • Replies: 4
    • Views: 240
    8th June 2019, 23:39 Go to last post
    • Replies: 4
    • Views: 304
    7th June 2019, 20:17 Go to last post