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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 3,207
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 30,773
    klug
    3rd December 2007, 18:00 Go to last post

  1. Current Reference in Sub-Threshold region

    Started by gokulpgk, 20th November 2019 17:35
    1 Attachment(s)
    • Replies: 3
    • Views: 187
    frankrose
    Yesterday, 23:48 Go to last post

  2. Temperature mobility degradation factor (c) - MOSFET SOI

    Started by lufer17, 16th November 2019 00:42
    • Replies: 2
    • Views: 236
    lufer17
    Yesterday, 18:54 Go to last post

  3. Problem in layout result of MOS pseudo resistor

    Started by Junus2012, Yesterday 14:18
    5 Attachment(s)
    • Replies: 1
    • Views: 79
    jjx
    Yesterday, 15:19 Go to last post

  4. on-resistance of a mosfet

    Started by SAMIRAZ, 19th October 2019 21:48
    • Replies: 2
    • Views: 339
    SAMIRAZ
    19th November 2019, 14:18 Go to last post

  5. Difference circuit not acting as expected

    Started by Hawaslsh, 19th November 2019 04:38
    3 Attachment(s)
    • Replies: 3
    • Views: 172
    FvM
    19th November 2019, 10:13 Go to last post

  6. "calibre view generation encountered a fatal error" but spectre PEX extraction works

    Started by OG_, 11th June 2019 15:48
    4 Attachment(s)
    • Replies: 14
    • Views: 1,864
    whedaboard
    19th November 2019, 06:48 Go to last post

  7. Calibre LVS Error with missing connection.

    Started by Trafford, 15th November 2019 21:44
    1 Attachment(s)
    • Replies: 1
    • Views: 184
    slizak
    17th November 2019, 20:16 Go to last post

  8. Fully-Differential folded cascode amplifier with enhanced gain

    Started by Junus2012, 7th November 2019 12:29
    3 Attachment(s)
    • Replies: 14
    • Views: 742
    sutapanaki
    15th November 2019, 19:25 Go to last post

  9. What are biasing circuits?

    Started by MubarakKhan, 14th November 2019 13:47
    • Replies: 2
    • Views: 190
    frankrose
    14th November 2019, 18:32 Go to last post

  10. Designing of a Digital to Analog converter

    Started by Prem Arjun, 13th November 2019 19:09
    1 Attachment(s)
    • Replies: 1
    • Views: 211
    deep_sea
    14th November 2019, 15:08 Go to last post

  11. Determining the sensitive volume in a MOSFET in SEU

    Started by msoleimaninia, 13th November 2019 16:55
    • Replies: 0
    • Views: 76
    msoleimaninia
    13th November 2019, 16:55 Go to last post

  12. Class AB fully differential amplifier design issue

    Started by Junus2012, 12th November 2019 17:13
    1 Attachment(s)
    • Replies: 3
    • Views: 264
    Junus2012
    13th November 2019, 12:29 Go to last post

  13. Tapered Buffer Peak Voltages

    Started by littlerock, 11th November 2019 11:41
    2 Attachment(s)
    • Replies: 0
    • Views: 176
    littlerock
    11th November 2019, 11:41 Go to last post

  14. Moved: [SOLVED] inverter output Vhigh voltage

    Started by AllenD, 11th November 2019 17:43
    •  
    •  

  15. DAC unit cap selection for SAR ADC

    Started by spswaroopa, 6th November 2019 12:20
    • Replies: 3
    • Views: 266
    timof
    9th November 2019, 02:38 Go to last post

  16. Resistor mismatch hand calculation and simulation

    Started by ashrafsazid, 5th November 2019 23:50
    1 Attachment(s)
    • Replies: 4
    • Views: 299
    wwfeldman
    7th November 2019, 17:14 Go to last post

  17. Rail to rail input folded operational amplifier

    Started by Junus2012, 7th November 2019 15:07
    1 Attachment(s)
    • Replies: 0
    • Views: 173
    Junus2012
    7th November 2019, 15:07 Go to last post

  18. Feasibility Analyses in Cadence

    Started by Junus2012, 7th November 2019 10:03
    • Replies: 0
    • Views: 144
    Junus2012
    7th November 2019, 10:03 Go to last post

  19. How to connect N_BPW_33RF switch in RF NMOS characterization in UMC 130nm process

    Started by anas171, 6th November 2019 04:26
    1 Attachment(s)
    • Replies: 1
    • Views: 145
    deep_sea
    6th November 2019, 11:05 Go to last post

  20. Capacitive Boost or Charge-Pump DC-DC Converter

    Started by WASDQWERTY, 23rd October 2019 11:08
    4 Attachment(s)
    • Replies: 8
    • Views: 599
    BradtheRad
    6th November 2019, 08:29 Go to last post

  21. Difference between NMOS/PMOS with and without Deep Nwell

    Started by hafis.m, 25th October 2019 09:52
    • Replies: 2
    • Views: 280
    dick_freebird
    6th November 2019, 02:55 Go to last post

  22. Analog Layout - Sharing source/drain

    Started by big_fudge98, 2nd November 2019 18:48
    • Replies: 1
    • Views: 258
    frankrose
    5th November 2019, 19:42 Go to last post

  23. Source follower design issue for cascoded two stage op-amp

    Started by Junus2012, 5th November 2019 16:26
    1 Attachment(s)
    • Replies: 0
    • Views: 139
    Junus2012
    5th November 2019, 16:26 Go to last post

  24. What does the NP stand for in SSGNP and FFGNP

    Started by janthonym, 4th November 2019 18:44
    • Replies: 0
    • Views: 141
    janthonym
    4th November 2019, 18:44 Go to last post

  25. While checking LVS I got following error LOGS

    Started by MubarakKhan, 4th November 2019 10:57
    • Replies: 0
    • Views: 181
    MubarakKhan
    4th November 2019, 10:57 Go to last post

  26. Modelling power supply for cadence simulations

    Started by big_fudge98, 3rd November 2019 13:16
    • Replies: 4
    • Views: 299
    frankrose
    3rd November 2019, 21:43 Go to last post

  27. RHP zero cancellation in miller compensated opamp

    Started by big_fudge98, 3rd November 2019 10:45
    • Replies: 2
    • Views: 224
    FvM
    3rd November 2019, 13:09 Go to last post

  28. MOSFET soi, to use LTSpice

    Started by lufer17, 2nd November 2019 15:27
    • Replies: 1
    • Views: 213
    dick_freebird
    2nd November 2019, 20:34 Go to last post

  29. Noise calculation in static-dynamic circuit

    Started by amr.maghraby, 31st October 2019 09:44
    • Replies: 3
    • Views: 241
    pancho_hideboo
    2nd November 2019, 19:15 Go to last post

  30. Relxpert model file which supports UMC65 for reliability simulation

    Started by abhishek260, 1st November 2019 09:19
    • Replies: 1
    • Views: 224
    ThisIsNotSam
    1st November 2019, 10:27 Go to last post
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