Service Notification

EDAboard.com Scheduled Maintenance for 6/4/2020

Starting at 12:00pm EST Thursday June 4th EDABoard will be in maintenance mode and be unavailable. The website is being migrated to a new web server and the software is being upgraded. With the large volume of data & images to move, migration is expected to last for 8 - 10 hours. When started the forum will go into maintenance mode and no posts, edits or registrations can be made.
  1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    131,720
Page 1 of 651 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 19513

Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 7,040
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 34,626
    klug
    3rd December 2007, 18:00 Go to last post

  1. Measurements of SNR and SFDR of ADC for different input frequencies

    Started by Chinmaye, 2nd June 2020 16:45
    • Replies: 9
    • Views: 374
    Puppet123
    Yesterday, 16:22 Go to last post

  2. Schematic circuit plot from Cadence Virtuoso

    Started by Junus2012, 31st May 2020 17:35
    5 Attachment(s)
    • Replies: 15
    • Views: 614
    Junus2012
    2nd June 2020, 19:44 Go to last post

  3. Rail to rail circuit simulation

    Started by ibiteee, 19th May 2020 15:35
    2 Attachment(s)
    • Replies: 10
    • Views: 661
    Easy peasy
    1st June 2020, 22:14 Go to last post

  4. Stuck at simulations of Amplifier in LTSpice

    Started by robi10101298, 25th May 2020 17:14
    4 Attachment(s)
    • Replies: 5
    • Views: 444
    Audioguru
    1st June 2020, 20:04 Go to last post

  5. [SOLVED] Biasing and sizing transistors in comparator circuit

    Started by solsopp, 31st May 2020 17:37
    2 Attachment(s)
    • Replies: 6
    • Views: 356
    sutapanaki
    1st June 2020, 19:26 Go to last post

  6. Well Proximity Effects (WPE): Is there any difference between PMOS and NMOS devices?

    Started by senmos, 31st May 2020 17:01
    • Replies: 1
    • Views: 246
    dick_freebird
    31st May 2020, 20:57 Go to last post

  7. Figure out the dimensions for this circuit button for mouse

    Started by lovingdemscience, 30th May 2020 07:24
    4 Attachment(s)
    • Replies: 4
    • Views: 413
    FvM
    30th May 2020, 11:23 Go to last post

  8. Link between sampling and accuracy

    Started by yefj, 26th May 2020 14:28
    1 Attachment(s)
    • Replies: 3
    • Views: 416
    Puppet123
    30th May 2020, 01:43 Go to last post

  9. Noise simulation of OPAmp

    Started by deep_sea, 28th May 2020 05:26
    3 Attachment(s)
    • Replies: 2
    • Views: 289
    jjx
    29th May 2020, 09:36 Go to last post

  10. How to connect WiFi ad BLE modules in implanted systems.

    Started by MSAKARIM, 3rd May 2020 16:33
    • Replies: 2
    • Views: 996
    ZoroZeng
    29th May 2020, 03:17 Go to last post

  11. Circuit Design using FinFETs

    Started by nidish, 25th May 2020 16:32
    • Replies: 2
    • Views: 211
    Puppet123
    26th May 2020, 05:28 Go to last post

  12. Time Interleaved ADC Filtering at Output

    Started by Puppet123, 23rd May 2020 22:40
    • Replies: 3
    • Views: 404
    sutapanaki
    24th May 2020, 23:13 Go to last post

  13. Need for safe phase margin when dealing with sin input signals

    Started by Junus2012, 22nd May 2020 22:04
    2 Attachment(s)
    • Replies: 8
    • Views: 486
    danadakk
    23rd May 2020, 21:47 Go to last post

  14. Bulk fixing (gluing) CMOS

    Started by lufer17, 23rd May 2020 14:49
    1 Attachment(s)
    • Replies: 1
    • Views: 227
    dick_freebird
    23rd May 2020, 18:46 Go to last post

  15. Verilog and VHDL noise modelling

    Started by deep_sea, 20th May 2020 12:28
    • Replies: 5
    • Views: 466
    ThisIsNotSam
    22nd May 2020, 11:14 Go to last post

  16. What are the typical lab characterization equipment used for testing Analog ICs?

    Started by doncarlosalbatros, 21st May 2020 01:20
    • Replies: 3
    • Views: 462
    t4_v
    21st May 2020, 09:07 Go to last post

  17. The stability of the power amplifier

    Started by OZZAA, 5th April 2020 08:01
    4 Attachment(s)
    • Replies: 3
    • Views: 575
    BigBoss
    20th May 2020, 01:01 Go to last post

  18. sizing of floating current sources in folded cascode amplifier ?

    Started by cmos_ajay, 18th May 2020 10:30
    2 Attachment(s)
    • Replies: 3
    • Views: 336
    t4_v
    19th May 2020, 10:13 Go to last post

  19. Simulating AC performance of the amplifier with switched capacitor circuit

    Started by Junus2012, 13th May 2020 23:40
    • Replies: 11
    • Views: 978
    LvW
    16th May 2020, 09:07 Go to last post

  20. Trends in Analog IP for ASIC Design

    Started by JElectric, 6th May 2020 12:46
    • Replies: 7
    • Views: 781
    Puppet123
    15th May 2020, 23:44 Go to last post

  21. Layout of big transistors

    Started by Junus2012, 14th May 2020 23:19
    • Replies: 3
    • Views: 381
    dick_freebird
    15th May 2020, 18:31 Go to last post

  22. Implementation of Operational Transconductance Amplifier in LTSpice

    Started by robi10101298, 7th May 2020 21:35
    5 Attachment(s)
    • Replies: 12
    • Views: 1,055
    t4_v
    15th May 2020, 10:52 Go to last post

  23. Biasing the amplifier with high current mirror ration

    Started by Junus2012, 10th May 2020 00:35
    2 Attachment(s)
    • Replies: 11
    • Views: 947
    Junus2012
    14th May 2020, 23:40 Go to last post

  24. [HSpice] Question about HSpice Simulation of Similar SRAM Column/Network

    Started by EEPuppyPuppy, 14th May 2020 05:06
    • Replies: 0
    • Views: 283
    EEPuppyPuppy
    14th May 2020, 05:06 Go to last post

  25. Matching the biasing circuit to the core amplifier

    Started by Junus2012, 2nd May 2020 22:07
    2 Pages •
    1 2
    8 Attachment(s)
    • Replies: 20
    • Views: 2,120
    Junus2012
    13th May 2020, 17:39 Go to last post

  26. Leakage currents in nano meter scale CMOS processes

    Started by hobbyiclearner, 5th May 2020 12:23
    • Replies: 7
    • Views: 1,680
    t4_v
    13th May 2020, 10:39 Go to last post

  27. SAR ADC Architecture Blocks

    Started by Adithya_Pai, 1st May 2020 19:40
    3 Attachment(s)
    • Replies: 5
    • Views: 1,337
    sutapanaki
    9th May 2020, 18:46 Go to last post

  28. Is this CMRR plot correct?

    Started by fat_123, 7th May 2020 21:19
    1 Attachment(s)
    • Replies: 3
    • Views: 482
    stenzer
    9th May 2020, 13:32 Go to last post

  29. Difference between Sample/Value Function in Cadence Spectre

    Started by Puppet123, 1st May 2020 05:18
    • Replies: 10
    • Views: 1,518
    vivekroy
    9th May 2020, 12:05 Go to last post

  30. CMOS differential OPAmp

    Started by MILIND_7, 18th March 2020 10:53
    • Replies: 5
    • Views: 753
    vivekroy
    9th May 2020, 10:13 Go to last post
Powered by vBulletin™
Copyright © 2017 vBulletin Solutions, Inc. All rights reserved.