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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 1,986
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 29,526
    klug
    3rd December 2007, 18:00 Go to last post

  1. Different connections to Common node in differential pair

    Started by circuitking, Yesterday 18:59
    1 Attachment(s)
    • Replies: 4
    • Views: 81
    BradtheRad
    Today, 03:43 Go to last post

  2. stretching the 0 pulse of a digital output with a certain T

    Started by iaf, 14th June 2019 14:01
    4 Attachment(s)
    • Replies: 18
    • Views: 496
    iaf
    Yesterday, 13:50 Go to last post

  3. PCB designing and wire bonding both

    Started by ICdesignerbeginner, Yesterday 07:11
    • Replies: 0
    • Views: 48
    ICdesignerbeginner
    Yesterday, 07:11 Go to last post

  4. Looking for 'Introduction to CMOS OP-AMPs and Comparators' ebook

    Started by hobbyiclearner, 23rd June 2019 20:05
    • Replies: 1
    • Views: 75
    dick_freebird
    23rd June 2019, 23:37 Go to last post

  5. Half Bridge driver veriloga model

    Started by michelebergo, 22nd June 2019 10:38
    • Replies: 0
    • Views: 96
    michelebergo
    22nd June 2019, 10:38 Go to last post

  6. Cadence 6.1.4 on CentOS (***** cadence)

    Started by Majid_Vatan_Parast, 21st June 2019 07:57
    1 Attachment(s)
    • Replies: 0
    • Views: 85
    Majid_Vatan_Parast
    21st June 2019, 07:57 Go to last post

  7. Analog Layout - Multipliers and Fingers

    Started by Puppet123, 21st June 2019 02:40
    • Replies: 1
    • Views: 98
    dick_freebird
    21st June 2019, 03:02 Go to last post

  8. Opamp Layout Example

    Started by Puppet123, 19th June 2019 18:05
    • Replies: 1
    • Views: 147
    BradtheRad
    20th June 2019, 05:32 Go to last post

  9. CMRR is less than the DC differential gain

    Started by Junus2012, 17th June 2019 18:24
    • Replies: 8
    • Views: 217
    Dominik Przyborowski
    19th June 2019, 18:29 Go to last post

  10. TSMC 65nm mocap_rf varactor

    Started by mahir, 18th June 2019 15:02
    • Replies: 1
    • Views: 145
    frankrose
    18th June 2019, 23:27 Go to last post

  11. "calibre view generation encountered a fatal error" but spectre PEX extraction works

    Started by OG_, 11th June 2019 15:48
    4 Attachment(s)
    • Replies: 12
    • Views: 708
    OG_
    18th June 2019, 21:12 Go to last post

  12. LC VCO with Capacitor filter, what is the cap doing?

    Started by mvj, 17th June 2019 11:37
    1 Attachment(s)
    • Replies: 2
    • Views: 168
    mvj
    18th June 2019, 14:31 Go to last post

  13. [SOLVED] measuring the parasitic capacitance at a certain node in cadence

    Started by amr.maghraby, 17th June 2019 14:23
    • Replies: 7
    • Views: 215
    ThisIsNotSam
    17th June 2019, 20:47 Go to last post

  14. Mismatch Contribution Analysis

    Started by rosaeidi, 17th June 2019 17:26
    • Replies: 1
    • Views: 101
    frankrose
    17th June 2019, 18:43 Go to last post

  15. PMOS WELL of same bulk potential of different transistor groups

    Started by Junus2012, 11th June 2019 17:41
    • Replies: 5
    • Views: 291
    sutapanaki
    13th June 2019, 00:37 Go to last post

  16. layout connection using different metalization layers

    Started by Junus2012, 11th June 2019 14:10
    • Replies: 7
    • Views: 242
    Junus2012
    12th June 2019, 23:03 Go to last post

  17. Port size in layout design

    Started by Junus2012, 11th June 2019 16:00
    • Replies: 4
    • Views: 190
    Junus2012
    12th June 2019, 23:01 Go to last post

  18. current mirror matching issue

    Started by Junus2012, 9th June 2019 18:55
    1 Attachment(s)
    • Replies: 7
    • Views: 321
    Junus2012
    12th June 2019, 22:49 Go to last post

  19. gate connection using poly vs metal

    Started by Junus2012, 9th June 2019 19:19
    1 Attachment(s)
    • Replies: 5
    • Views: 315
    dick_freebird
    11th June 2019, 23:15 Go to last post

  20. Drai and source via contact

    Started by Junus2012, 11th June 2019 14:01
    • Replies: 1
    • Views: 116
    Dominik Przyborowski
    11th June 2019, 20:40 Go to last post

  21. guard ring contacts for the PMOS transistors

    Started by Junus2012, 11th June 2019 13:59
    • Replies: 1
    • Views: 103
    ljp2706
    11th June 2019, 16:17 Go to last post

  22. Layout Abutment Sitting in the TSMC PDK

    Started by JAVAD_B, 11th June 2019 09:46
    1 Attachment(s)
    • Replies: 3
    • Views: 171
    ljp2706
    11th June 2019, 16:11 Go to last post

  23. TSMC 65nm Inductor Finder Parameters

    Started by mahir, 10th June 2019 15:21
    • Replies: 2
    • Views: 129
    mahir
    11th June 2019, 08:25 Go to last post

  24. Run Veriloga demo in hspice 2013.03-SP2 error

    Started by yyy963741tw, 11th June 2019 08:19
    2 Attachment(s)
    • Replies: 0
    • Views: 102
    yyy963741tw
    11th June 2019, 08:19 Go to last post

  25. [SOLVED] How to calculate the input-refered noise for two OTA in parallel?

    Started by nidare, 9th June 2019 16:43
    • Replies: 4
    • Views: 284
    nidare
    10th June 2019, 11:41 Go to last post

  26. Plotting waveform in Mathlab from Cadence

    Started by Junus2012, 15th May 2019 22:11
    • Replies: 5
    • Views: 1,041
    ljp2706
    9th June 2019, 22:04 Go to last post

  27. Pin definition in TSMC 0.18um

    Started by JAVAD_B, 7th June 2019 14:15
    • Replies: 4
    • Views: 297
    JAVAD_B
    9th June 2019, 07:46 Go to last post

  28. devideing large MOSFET gate using muti fingers

    Started by Junus2012, 7th June 2019 18:05
    • Replies: 4
    • Views: 240
    Dominik Przyborowski
    8th June 2019, 23:39 Go to last post

  29. When was Cadence Maestro introduced into Cadence Virtuoso ?

    Started by Puppet123, 11th December 2018 05:31
    • Replies: 2
    • Views: 516
    pancho_hideboo
    8th June 2019, 19:19 Go to last post

  30. decoupling capacitors in integrated circuit design

    Started by Junus2012, 5th June 2019 20:37
    • Replies: 4
    • Views: 313
    ljp2706
    7th June 2019, 20:17 Go to last post
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