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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 236
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 27,916
    klug
    3rd December 2007, 18:00 Go to last post

  1. "np" layer and "pp" layer in CMOS circuit

    Started by AllenD, 12th July 2018 04:39
    1 Attachment(s)
    • Replies: 4
    • Views: 165
    AllenD
    Yesterday, 03:55 Go to last post

  2. Fully differential Amplifier class AB

    Started by hannover90, 12th July 2018 18:24
    • Replies: 1
    • Views: 105
    erikl
    14th July 2018, 20:50 Go to last post

  3. Question about the changing of Gate terminal material

    Started by quyleanh, 13th July 2018 03:17
    • Replies: 1
    • Views: 159
    dick_freebird
    14th July 2018, 03:02 Go to last post

  4. Disable to read "cds.lib" in Ocean Run.

    Started by pancho_hideboo, 7th July 2018 06:12
    • Replies: 3
    • Views: 273
    erikl
    13th July 2018, 16:27 Go to last post

  5. Calibre PEX error during generating calibre view

    Started by vieha007Electronic, 10th July 2018 00:28
    • Replies: 2
    • Views: 122
    vieha007Electronic
    12th July 2018, 23:24 Go to last post

  6. Issues around ads keysight layout

    Started by adeniyiMokesioluwa, 7th July 2018 12:03
    2 Attachment(s)
    • Replies: 1
    • Views: 118
    johnjoe
    12th July 2018, 11:07 Go to last post

  7. Simples current mirror input impedance

    Started by CAMALEAO, 10th July 2018 17:16
    1 Attachment(s)
    • Replies: 7
    • Views: 218
    CAMALEAO
    12th July 2018, 10:34 Go to last post

  8. Pipeline last stage gain

    Started by shanmei, 12th July 2018 03:04
    1 Attachment(s)
    • Replies: 0
    • Views: 63
    shanmei
    12th July 2018, 03:04 Go to last post

  9. [SOLVED] How can I calculate the (W/L) ratio for nmos and pmos in below schematics?

    Started by viny9694, 9th July 2018 01:38
    2 Attachment(s)
    • Replies: 1
    • Views: 210
    dick_freebird
    10th July 2018, 19:22 Go to last post

  10. DRC Errors after No Geometry Violations

    Started by Mahmoud_Dagher, 29th June 2018 11:32
    • Replies: 9
    • Views: 253
    dick_freebird
    10th July 2018, 19:09 Go to last post

  11. How to calculate the individual widths from total width for mosfet's?

    Started by viny9694, 9th July 2018 23:55
    2 Attachment(s)
    • Replies: 1
    • Views: 68
    dick_freebird
    10th July 2018, 06:29 Go to last post

  12. Exporting from CST and Importing to ALtium

    Started by f_t, 6th July 2018 18:20
    1 Attachment(s)
    • Replies: 3
    • Views: 154
    pragash
    10th July 2018, 01:51 Go to last post

  13. [SOLVED] Help pls! n+sd to psub spacing must be <=10um error!

    Started by Enorize, 27th June 2018 00:29
    2 Attachment(s)
    • Replies: 7
    • Views: 289
    erikl
    9th July 2018, 20:08 Go to last post

  14. Verilog-a cyclically dependent error

    Started by heba_saleh, 8th July 2018 11:20
    • Replies: 3
    • Views: 148
    pancho_hideboo
    9th July 2018, 01:14 Go to last post

  15. How to do layout of a group of capacitor around 300 please?

    Started by Enorize, 27th June 2018 13:38
    • Replies: 8
    • Views: 312
    dick_freebird
    9th July 2018, 01:12 Go to last post

  16. [SOLVED] Monte Carlo Simulation in HSPICE 2008.03

    Started by rmanalo, 6th July 2018 06:07
    1 Attachment(s)
    • Replies: 3
    • Views: 198
    erikl
    7th July 2018, 23:08 Go to last post

  17. Moved: [Moved]: Verilog code to read .txt (hexa value)file and and to store in PC

    Started by vachanukb, 6th July 2018 19:41
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  18. What's the purpose the bias on the left two branches in this CMFB circuit

    Started by monglebest, 6th July 2018 17:37
    1 Attachment(s)
    • Replies: 1
    • Views: 103
    d123
    6th July 2018, 19:21 Go to last post

  19. Noise figure calculation in cadence virtuoso

    Started by pallabeebsws92, 6th July 2018 14:48
    • Replies: 0
    • Views: 74
    pallabeebsws92
    6th July 2018, 14:48 Go to last post

  20. [SOLVED] What it the Output Template for mobility, un

    Started by rmanalo, 3rd July 2018 07:59
    4 Attachment(s)
    • Replies: 3
    • Views: 145
    erikl
    5th July 2018, 22:35 Go to last post

  21. DRC metal density issue. How to fix it?

    Started by shanmei, 1st July 2018 20:11
    • Replies: 6
    • Views: 273
    rangermad
    5th July 2018, 15:08 Go to last post

  22. [SOLVED] HSPICE Data to Excel

    Started by rmanalo, 4th July 2018 13:01
    • Replies: 3
    • Views: 163
    pancho_hideboo
    5th July 2018, 12:56 Go to last post

  23. Problem in IP3 simulation of an entire receiver in cadence virtuoso

    Started by EhsanHamzei, 4th July 2018 12:27
    1 Attachment(s)
    • Replies: 5
    • Views: 166
    pancho_hideboo
    5th July 2018, 12:32 Go to last post

  24. [SOLVED] Technology Constants Estimation

    Started by rmanalo, 22nd June 2018 13:14
    1 Attachment(s)
    • Replies: 2
    • Views: 240
    abu_bua
    4th July 2018, 22:34 Go to last post

  25. Inversion Coefficient Usage

    Started by pedrovfr, 26th June 2018 02:16
    • Replies: 1
    • Views: 152
    abu_bua
    4th July 2018, 22:17 Go to last post

  26. SPWM H-Bridge Output Issues [Giving Square Wave Output]

    Started by Power_Pro123, 2nd July 2018 15:58
    5 Attachment(s)
    • Replies: 7
    • Views: 228
    BradtheRad
    4th July 2018, 03:07 Go to last post

  27. Mask Fabrication Workflow

    Started by melkord, 3rd July 2018 13:39
    • Replies: 1
    • Views: 95
    erikl
    3rd July 2018, 19:35 Go to last post

  28. Cadence Plotting/Calculator Question

    Started by ljp2706, 3rd July 2018 14:36
    • Replies: 3
    • Views: 129
    pancho_hideboo
    3rd July 2018, 16:06 Go to last post

  29. Discrete Time Sigma Delta ADC

    Started by Puppet123, 2nd July 2018 09:19
    1 Attachment(s)
    • Replies: 2
    • Views: 139
    Puppet123
    2nd July 2018, 20:19 Go to last post

  30. CMOS 0.18um 100 dB DC gain 1GHz UGB and rail-to-rail input stage opamp design

    Started by azizbaskan, 12th May 2018 19:03
    • Replies: 5
    • Views: 629
    c_oonnnn
    2nd July 2018, 05:58 Go to last post
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