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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 121
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 27,800
    klug
    3rd December 2007, 18:00 Go to last post

  1. IC design and MOSIS C5 technology for newbie

    Started by clros, 26th May 2018 08:13
    • Replies: 2
    • Views: 133
    clros
    Yesterday, 08:44 Go to last post

  2. Transient response of DC-DC buck converter

    Started by chandlerbing65nm, 26th May 2018 14:35
    3 Attachment(s)
    • Replies: 1
    • Views: 87
    dick_freebird
    26th May 2018, 18:30 Go to last post

  3. 2 phase Nonoverlapping clock generation can't not delay

    Started by sa126997, 24th May 2018 14:58
    2 Attachment(s)
    • Replies: 1
    • Views: 170
    jjx
    25th May 2018, 13:14 Go to last post

  4. What do calibre PERC tools do ?

    Started by Electric_Shock, 24th May 2018 03:59
    • Replies: 0
    • Views: 66
    Electric_Shock
    24th May 2018, 03:59 Go to last post

  5. Input-referred offsets in gm circuit cells

    Started by promach, 23rd May 2018 13:33
    1 Attachment(s)
    • Replies: 1
    • Views: 84
    frankrose
    23rd May 2018, 16:33 Go to last post

  6. MDAC for a Pipelined-SAR ADC

    Started by Majid_Vatan_Parast, 22nd May 2018 06:55
    1 Attachment(s)
    • Replies: 3
    • Views: 127
    dick_freebird
    22nd May 2018, 19:57 Go to last post

  7. Schematic Extraction of Standard Cells and AMS

    Started by ranaya, 22nd May 2018 11:26
    • Replies: 1
    • Views: 89
    dick_freebird
    22nd May 2018, 19:54 Go to last post

  8. Problem with icl7107 and opamp

    Started by vukhanh97na, 19th May 2018 10:00
    2 Attachment(s)
    • Replies: 6
    • Views: 236
    d123
    19th May 2018, 19:34 Go to last post

  9. PLL based CDR stability problem

    Started by i.burmistrov, 18th May 2018 18:00
    3 Attachment(s)
    • Replies: 0
    • Views: 126
    i.burmistrov
    18th May 2018, 18:00 Go to last post

  10. [SOLVED] Calibre Parasitic Extraction of TSMC018 Gate-Driver

    Started by JEOvergaard, 5th May 2018 11:22
    • Replies: 13
    • Views: 519
    timof
    18th May 2018, 02:21 Go to last post

  11. Hierarchical schematics in Data Sheet of Cadence ADE-XL and ADE-Explorer

    Started by pancho_hideboo, 17th May 2018 16:44
    • Replies: 0
    • Views: 84
    pancho_hideboo
    17th May 2018, 16:44 Go to last post

  12. Digital blocks with Verilog code

    Started by younes.Ng, 15th May 2018 17:59
    • Replies: 1
    • Views: 131
    jjx
    16th May 2018, 07:16 Go to last post

  13. How to make an integrator with vcvs(ideal opamp)

    Started by Darylpan, 15th May 2018 14:57
    3 Attachment(s)
    • Replies: 4
    • Views: 148
    dick_freebird
    15th May 2018, 19:04 Go to last post

  14. MMWave Layout Issues in CMOS

    Started by Puppet123, 19th April 2018 02:30
    2 Attachment(s)
    • Replies: 11
    • Views: 708
    Puppet123
    14th May 2018, 20:31 Go to last post

  15. Analog layout Shielding with VDD and VSS

    Started by RohithRaj, 11th May 2018 06:23
    • Replies: 4
    • Views: 231
    rangermad
    14th May 2018, 14:50 Go to last post

  16. CMOS 0.18um 100 dB DC gain 1GHz UGB and rail-to-rail input stage opamp design

    Started by azizbaskan, 12th May 2018 19:03
    • Replies: 4
    • Views: 405
    Dominik Przyborowski
    13th May 2018, 15:49 Go to last post

  17. 3rd order butterworth bandpass filter corners simulation

    Started by sherif96, 8th May 2018 20:09
    21 Attachment(s)
    • Replies: 13
    • Views: 490
    jjx
    13th May 2018, 15:25 Go to last post

  18. Moved: Capacitor bank for filter

    Started by sherif96, 12th May 2018 13:33
    •  
    •  

  19. Common Centroid: AB-AB or ABBA-BAAB

    Started by christofhapp, 27th April 2018 09:29
    1 Attachment(s)
    • Replies: 1
    • Views: 169
    jjx
    12th May 2018, 11:24 Go to last post

  20. ahdlLib doesn't work

    Started by Darylpan, 9th May 2018 16:47
    2 Attachment(s)
    • Replies: 13
    • Views: 467
    pancho_hideboo
    11th May 2018, 00:59 Go to last post

  21. PEX C capacitance - Huge delay in postlayout simulation

    Started by AlQadasi, 2nd May 2018 09:25
    2 Attachment(s)
    • Replies: 2
    • Views: 207
    timof
    9th May 2018, 18:36 Go to last post

  22. Mismatch simulation Schematic vs. Layout

    Started by DefconNowhere, 19th April 2018 16:23
    • Replies: 7
    • Views: 524
    timof
    9th May 2018, 18:33 Go to last post

  23. Moved: Using Allpass Filter as 90 degree phase shift

    Started by Fikadu, 9th May 2018 06:08
    •  
    •  

  24. Importing FinFET models from hspice

    Started by V.Singh, 6th May 2018 18:39
    • Replies: 3
    • Views: 251
    erikl
    8th May 2018, 20:52 Go to last post

  25. Layout of Differential Opamp

    Started by Puppet123, 5th May 2018 05:58
    2 Attachment(s)
    • Replies: 4
    • Views: 320
    erikl
    8th May 2018, 20:25 Go to last post

  26. Multilayer inductor parameter measurement with VNA

    Started by Martynas JankÅ«nas, 3rd May 2018 20:48
    3 Attachment(s)
    • Replies: 2
    • Views: 249
    Martynas Jankūnas
    7th May 2018, 21:11 Go to last post

  27. Which models for Huijsing's book "Operational Amplifiers: Theory and Design"?

    Started by spectrallypure, 4th May 2018 20:39
    1 Attachment(s)
    • Replies: 2
    • Views: 182
    erikl
    6th May 2018, 18:50 Go to last post

  28. MMWave Cross Coupled CMOS VCO Layouts

    Started by Puppet123, 24th April 2018 20:06
    3 Attachment(s)
    • Replies: 5
    • Views: 433
    BigBoss
    5th May 2018, 19:56 Go to last post

  29. Common Centroid Capacitor Layout in Cadence

    Started by Puppet123, 17th April 2018 22:22
    2 Attachment(s)
    • Replies: 5
    • Views: 540
    erikl
    5th May 2018, 14:33 Go to last post

  30. Noise due to passive resistor in Cadence Virtuoso

    Started by deveshkm, 1st May 2018 20:59
    • Replies: 4
    • Views: 246
    BigBoss
    4th May 2018, 22:46 Go to last post
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