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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 315
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 27,981
    klug
    3rd December 2007, 18:00 Go to last post

  1. Pdiff guard ring around nmos4?

    Started by MaryF, Yesterday 15:13
    • Replies: 1
    • Views: 74
    dick_freebird
    Yesterday, 20:54 Go to last post

  2. PTAT Current Source low slope

    Started by Ata_sa16, Yesterday 03:24
    4 Attachment(s)
    • Replies: 5
    • Views: 197
    Ata_sa16
    Yesterday, 20:09 Go to last post

  3. [SOLVED] What's the difference between stacked and cascode configurations?

    Started by Fávero Santos, 18th July 2018 00:12
    1 Attachment(s)
    • Replies: 3
    • Views: 280
    Ata_sa16
    Yesterday, 06:55 Go to last post

  4. Folded cascode output resistance

    Started by khaled2k, 17th August 2018 10:51
    1 Attachment(s)
    • Replies: 3
    • Views: 223
    Ata_sa16
    Yesterday, 03:16 Go to last post

  5. How to set the limit of probed shapes in virtuoso Layout GXL?

    Started by MaryF, 20th August 2018 11:06
    • Replies: 0
    • Views: 76
    MaryF
    20th August 2018, 11:06 Go to last post

  6. Layout GXL MPP GRs editing, max number of probed shapes reached

    Started by MaryF, 20th August 2018 10:42
    • Replies: 0
    • Views: 28
    MaryF
    20th August 2018, 10:42 Go to last post

  7. Spirals/TSMC 65nm CMOS

    Started by Puppet123, 19th August 2018 11:00
    • Replies: 0
    • Views: 120
    Puppet123
    19th August 2018, 11:00 Go to last post

  8. Neural network implementation using VLSI

    Started by Udit_agarwal, 15th August 2018 18:25
    • Replies: 1
    • Views: 178
    nmag
    18th August 2018, 02:06 Go to last post

  9. How to sweep Threshold Voltage using .pm model file?

    Started by npsnpsnps, 17th August 2018 13:29
    • Replies: 0
    • Views: 137
    npsnpsnps
    17th August 2018, 13:29 Go to last post

  10. Resistor Layout - Unit Cell Selection

    Started by Puppet123, 14th August 2018 17:29
    • Replies: 3
    • Views: 190
    rangermad
    17th August 2018, 13:29 Go to last post

  11. Building a solar cell 18650 battery charger + a voltage output circuit

    Started by adwnis123, 15th August 2018 21:58
    • Replies: 2
    • Views: 255
    BradtheRad
    17th August 2018, 04:12 Go to last post

  12. Mixed IC Design Flow Using: Synopsys DC-ICC & Cadence Virtuoso

    Started by ryu_hayabusa, 17th August 2018 03:37
    • Replies: 0
    • Views: 67
    ryu_hayabusa
    17th August 2018, 03:37 Go to last post

  13. Problem with plotting bathtub curve in ads

    Started by ultrasonic.1991, 14th August 2018 21:35
    2 Attachment(s)
    • Replies: 0
    • Views: 139
    ultrasonic.1991
    14th August 2018, 21:35 Go to last post

  14. questions about eye diagram of transimpedance amplifier

    Started by ultrasonic.1991, 1st August 2018 12:33
    11 Attachment(s)
    • Replies: 14
    • Views: 735
    KlausST
    14th August 2018, 07:36 Go to last post

  15. Layout of complementary clock signal trace

    Started by AllenD, 13th August 2018 05:54
    • Replies: 1
    • Views: 173
    cariban
    13th August 2018, 09:31 Go to last post

  16. Two stage operational amplifier

    Started by Green_Ic, 12th August 2018 12:57
    1 Attachment(s)
    • Replies: 2
    • Views: 184
    dick_freebird
    12th August 2018, 18:59 Go to last post

  17. SKILL Language: Meaning of "Hi"

    Started by XDJ_HBT, 11th August 2018 17:07
    • Replies: 2
    • Views: 262
    XDJ_HBT
    12th August 2018, 13:38 Go to last post

  18. TSMC 65nm Pad Issues

    Started by Puppet123, 11th August 2018 00:15
    • Replies: 0
    • Views: 173
    Puppet123
    11th August 2018, 00:15 Go to last post

  19. Virtuoso ADEXL Calculator Question

    Started by ljp2706, 8th August 2018 20:42
    • Replies: 1
    • Views: 201
    Dominik Przyborowski
    9th August 2018, 20:02 Go to last post

  20. Top level IO cells connection (multiple IO voltages and global source use) and ESD

    Started by NikosTS, 3rd August 2018 14:57
    2 Pages •
    1 2
    6 Attachment(s)
    • Replies: 22
    • Views: 703
    dick_freebird
    8th August 2018, 22:48 Go to last post

  21. Mosfet working in sub-threshold region

    Started by AllenD, 29th July 2018 07:14
    • Replies: 4
    • Views: 317
    dr_kca
    8th August 2018, 12:41 Go to last post

  22. PEX LVS ERROR: Ground Net not defined

    Started by s_babayan, 7th August 2018 13:56
    • Replies: 1
    • Views: 96
    dr_kca
    8th August 2018, 12:22 Go to last post

  23. How to optimize all transistors' size (length and width) in Cadence software?

    Started by Chaoping, 3rd August 2018 03:45
    • Replies: 4
    • Views: 230
    khaled2k
    8th August 2018, 11:57 Go to last post

  24. Reliability question for a casode 3.3V buffer using 1.8V MOS.

    Started by dr_kca, 6th August 2018 15:14
    1 Attachment(s)
    • Replies: 3
    • Views: 186
    khaled2k
    8th August 2018, 11:53 Go to last post

  25. TSMC 0.18um CMOS Tech - Question on Maturity

    Started by rmanalo, 8th August 2018 09:57
    • Replies: 1
    • Views: 103
    khaled2k
    8th August 2018, 10:02 Go to last post

  26. I want to learn FPGA board design

    Started by ali_umair21, 7th August 2018 18:45
    • Replies: 4
    • Views: 182
    KlausST
    8th August 2018, 06:37 Go to last post

  27. Importing Files from ASITIC (CIF files) Into Cadence

    Started by Puppet123, 4th August 2018 01:15
    1 Attachment(s)
    • Replies: 3
    • Views: 345
    Puppet123
    7th August 2018, 23:07 Go to last post

  28. L-edit technology file

    Started by yashfaith, 7th August 2018 16:37
    1 Attachment(s)
    • Replies: 0
    • Views: 87
    yashfaith
    7th August 2018, 16:37 Go to last post

  29. question about input impedance of transimpedance amplifier

    Started by ultrasonic.1991, 7th August 2018 14:50
    • Replies: 1
    • Views: 104
    pancho_hideboo
    7th August 2018, 15:33 Go to last post

  30. Boost regulator for 3.6V

    Started by Kick, 6th August 2018 07:39
    1 Attachment(s)
    • Replies: 3
    • Views: 160
    Kick
    7th August 2018, 06:19 Go to last post
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