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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 181
    1st May 2018, 14:19 Go to last post
  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 27,853
    3rd December 2007, 18:00 Go to last post
  1. Plot lambda vs length in Cadence

    Started by bharath_k, Today 19:20
    • Replies: 3
    • Views: 46
    Today, 22:52 Go to last post
  2. Folded cascode OTA design

    Started by Shishira, 18th June 2018 11:31
    • Replies: 11
    • Views: 334
    Today, 16:21 Go to last post
  3. Technology Constants Estimation

    Started by rmanalo, Today 13:14
    • Replies: 0
    • Views: 64
    Today, 13:14 Go to last post
    • Replies: 1
    • Views: 57
    Yesterday, 07:09 Go to last post
  4. [SOLVED] LVS problem when adding a DNW to HV NMOS in TSMC 65nm

    Started by aletar, 19th June 2018 16:03
    • Replies: 3
    • Views: 104
    20th June 2018, 15:12 Go to last post
  5. extract the dc current

    Started by shanmei, 20th June 2018 01:10
    • Replies: 4
    • Views: 122
    20th June 2018, 06:54 Go to last post
  6. Floating Stimuli in ADE/ADEXL

    Started by ljp2706, 19th June 2018 18:25
    • Replies: 2
    • Views: 72
    20th June 2018, 03:37 Go to last post
  7. [HSpice] Invertor Simulation Problem

    Started by EEPuppyPuppy, 17th June 2018 22:37
    • Replies: 2
    • Views: 144
    18th June 2018, 01:44 Go to last post
    • Replies: 0
    • Views: 95
    17th June 2018, 11:31 Go to last post
  8. [SOLVED] HSpice error: missing library entry name

    Started by EEPuppyPuppy, 14th June 2018 18:26
    • Replies: 4
    • Views: 205
    17th June 2018, 11:20 Go to last post
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  9. Spice model to VLSI

    Started by clros, 15th June 2018 12:08
    • Replies: 4
    • Views: 189
    16th June 2018, 12:55 Go to last post
  10. NMOS and PMOS W/L Ratio

    Started by hetang0503, 14th June 2018 12:30
    • Replies: 2
    • Views: 143
    16th June 2018, 01:10 Go to last post
    • Replies: 5
    • Views: 390
    15th June 2018, 23:21 Go to last post
  11. MAGIC real technology files

    Started by okguy, 14th June 2018 20:11
    • Replies: 2
    • Views: 162
    15th June 2018, 02:21 Go to last post
    • Replies: 8
    • Views: 395
    14th June 2018, 03:07 Go to last post
  12. ADS Layout to Cadence Layout

    Started by Puppet123, 13th June 2018 15:00
    • Replies: 0
    • Views: 96
    13th June 2018, 15:00 Go to last post
  13. [SOLVED] Import a cell library into cadence virtuoso

    Started by Mahmoud_Dagher, 12th June 2018 17:42
    • Replies: 1
    • Views: 87
    12th June 2018, 18:20 Go to last post
  14. How can I Draw Layout of CNTFET.

    Started by MUKESHBEG, 12th June 2018 17:04
    • Replies: 0
    • Views: 69
    12th June 2018, 17:04 Go to last post
  15. [SOLVED] Bondpad and Chip Guardring connection GF BiCMOS 130nm

    Started by adancy24, 11th June 2018 13:33
    • Replies: 2
    • Views: 132
    11th June 2018, 15:36 Go to last post
  16. In chip integrated decoupling capacitors

    Started by strabush, 10th June 2018 14:26
    • Replies: 2
    • Views: 191
    11th June 2018, 03:53 Go to last post
  17. Common Mode Feedback

    Started by Majid_Vatan_Parast, 6th June 2018 15:12
    • Replies: 12
    • Views: 495
    7th June 2018, 15:34 Go to last post
    • Replies: 5
    • Views: 321
    6th June 2018, 10:45 Go to last post
  18. Binary weighted switch for r-2r DAC

    Started by mburakbaran, 1st June 2018 12:16
    • Replies: 12
    • Views: 556
    4th June 2018, 17:29 Go to last post
    • Replies: 2
    • Views: 198
    4th June 2018, 12:57 Go to last post
  19. TSMC 65nm Substrate Issues

    Started by Puppet123, 2nd June 2018 22:05
    • Replies: 1
    • Views: 171
    4th June 2018, 03:46 Go to last post