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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 2,904
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 30,452
    klug
    3rd December 2007, 18:00 Go to last post

  1. Output of Nand Sequential based Phase-Frequency Detector

    Started by firasgany7, Today 14:20
    2 Attachment(s)
    • Replies: 1
    • Views: 47
    FvM
    Today, 18:07 Go to last post

  2. Problem in saving data during DC sweep simulation in Cadence Virtuoso

    Started by Junus2012, 10th October 2019 18:24
    1 Attachment(s)
    • Replies: 6
    • Views: 313
    Junus2012
    Yesterday, 18:33 Go to last post

  3. Need documets related to extraction of Inductance using Cadence Assura

    Started by sp.bhuvana, 14th May 2019 11:41
    • Replies: 4
    • Views: 391
    Puppet123
    Yesterday, 02:48 Go to last post

  4. NCSU FreePDK 15nm for Analog Design

    Started by Puppet123, 7th October 2019 21:43
    • Replies: 2
    • Views: 194
    Puppet123
    Yesterday, 02:35 Go to last post

  5. CMOS FINFET Layout Tutorials/Explanations

    Started by Puppet123, 10th October 2019 19:00
    • Replies: 8
    • Views: 278
    Puppet123
    Yesterday, 02:29 Go to last post

  6. Abbreviations of Layers in 65nm LSW

    Started by KingDarius6288, 25th August 2019 00:47
    • Replies: 2
    • Views: 274
    timof
    11th October 2019, 07:30 Go to last post

  7. Optimized MinCap, Minres values for 10 MHz amp simulation using Spectre

    Started by Luis_rr, 9th October 2019 08:59
    • Replies: 3
    • Views: 213
    timof
    11th October 2019, 07:25 Go to last post

  8. Transistor region of operation in operational amplifier

    Started by Junus2012, 30th September 2019 17:53
    8 Attachment(s)
    • Replies: 17
    • Views: 847
    sutapanaki
    10th October 2019, 20:00 Go to last post

  9. Too large .psf file generated by Post layout simulation using Spectre

    Started by Luis_rr, 9th October 2019 08:51
    • Replies: 1
    • Views: 159
    pancho_hideboo
    9th October 2019, 11:16 Go to last post

  10. What are the layout methods to make source to drain capacitance zero?

    Started by saran826, 6th October 2019 06:53
    • Replies: 3
    • Views: 289
    timof
    6th October 2019, 23:13 Go to last post

  11. What things we need to take care a lenghty routing let's say 5000um

    Started by saran826, 6th October 2019 06:24
    • Replies: 0
    • Views: 155
    saran826
    6th October 2019, 06:24 Go to last post

  12. [SOLVED] Common mode gain simulation for differential amplifier using balun

    Started by Junus2012, 18th September 2019 09:58
    1 Attachment(s)
    • Replies: 3
    • Views: 333
    erikl
    4th October 2019, 21:14 Go to last post

  13. Input referred noise simulation for OP-amp

    Started by Junus2012, 3rd October 2019 12:02
    1 Attachment(s)
    • Replies: 5
    • Views: 296
    FvM
    3rd October 2019, 22:41 Go to last post

  14. Decoupling Capacitance in IC Layo

    Started by Puppet123, 28th September 2019 05:03
    • Replies: 5
    • Views: 516
    Puppet123
    2nd October 2019, 14:55 Go to last post

  15. Overdrive voltage relationship to the op-amp speed

    Started by Junus2012, 27th September 2019 20:28
    • Replies: 8
    • Views: 453
    asdf44
    1st October 2019, 20:30 Go to last post

  16. Rplpoly layout matching problem

    Started by agarwalneeraj1, 21st September 2019 08:08
    • Replies: 5
    • Views: 399
    timof
    1st October 2019, 04:08 Go to last post

  17. differential amplifier design using ngspice

    Started by prateek3790, 28th September 2019 15:54
    2 Attachment(s)
    • Replies: 5
    • Views: 267
    vivekroy
    29th September 2019, 16:52 Go to last post

  18. SFDR of DAC obtained from its INL and DNL

    Started by shanmei, 29th September 2019 03:35
    • Replies: 2
    • Views: 204
    Dominik Przyborowski
    29th September 2019, 14:14 Go to last post

  19. Speed relationship to the operational amplifier speed

    Started by Junus2012, 27th September 2019 20:22
    • Replies: 1
    • Views: 140
    dick_freebird
    27th September 2019, 20:33 Go to last post

  20. Design consideration of CMOS anti aliasing filter

    Started by Junus2012, 25th September 2019 19:01
    • Replies: 2
    • Views: 268
    Junus2012
    27th September 2019, 14:59 Go to last post

  21. -3db frequency of the op-amp open loop gain

    Started by Junus2012, 23rd September 2019 19:18
    • Replies: 11
    • Views: 639
    asdf44
    27th September 2019, 14:51 Go to last post

  22. How to determine tone 1 and tone 2 in ADE IIP3 simulation (hb) for a 60 GHz LNA?

    Started by JLHW, 26th September 2019 05:13
    2 Attachment(s)
    • Replies: 12
    • Views: 436
    JLHW
    27th September 2019, 14:16 Go to last post

  23. Spice .INC file into Cadence Spectre/DFII

    Started by Puppet123, 26th September 2019 22:34
    • Replies: 3
    • Views: 201
    dick_freebird
    27th September 2019, 03:44 Go to last post

  24. Parasitic capacitor extraction: huge value

    Started by Anomis, 30th May 2019 10:08
    2 Attachment(s)
    • Replies: 9
    • Views: 781
    circuitking
    27th September 2019, 01:49 Go to last post

  25. [SOLVED] Connecting the load to VCM or to ground in single supply operation

    Started by Junus2012, 23rd September 2019 16:08
    • Replies: 4
    • Views: 297
    BradtheRad
    25th September 2019, 02:36 Go to last post

  26. [SOLVED] Single or dual supply operation

    Started by Junus2012, 24th September 2019 12:52
    • Replies: 2
    • Views: 225
    KlausST
    24th September 2019, 22:22 Go to last post

  27. ConnectLib files in ams simulation Cadence

    Started by Chinmaye, 15th September 2019 19:19
    • Replies: 1
    • Views: 258
    erikl
    24th September 2019, 19:03 Go to last post

  28. What is Double Snapback Characteristics in High-Voltage nMOSFETs

    Started by MubarakKhan, 23rd September 2019 07:41
    1 Attachment(s)
    • Replies: 2
    • Views: 216
    erikl
    24th September 2019, 18:52 Go to last post

  29. Length of Path in Cadence Virtuoso/DFII

    Started by Puppet123, 23rd September 2019 21:22
    • Replies: 1
    • Views: 163
    rangermad
    24th September 2019, 13:06 Go to last post

  30. deviding Y value by X values in Cadence Virtuoso calculator

    Started by Junus2012, 17th September 2019 16:29
    7 Attachment(s)
    • Replies: 10
    • Views: 578
    Junus2012
    23rd September 2019, 16:53 Go to last post
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