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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 315
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 27,979
    klug
    3rd December 2007, 18:00 Go to last post

  1. How to set the limit of probed shapes in virtuoso Layout GXL?

    Started by MaryF, Today 11:06
    • Replies: 0
    • Views: 38
    MaryF
    Today, 11:06 Go to last post

  2. Layout GXL MPP GRs editing, max number of probed shapes reached

    Started by MaryF, Today 10:42
    • Replies: 0
    • Views: 15
    MaryF
    Today, 10:42 Go to last post

  3. Spirals/TSMC 65nm CMOS

    Started by Puppet123, Yesterday 11:00
    • Replies: 0
    • Views: 108
    Puppet123
    Yesterday, 11:00 Go to last post

  4. Folded cascode output resistance

    Started by khaled2k, 17th August 2018 10:51
    1 Attachment(s)
    • Replies: 2
    • Views: 200
    frankrose
    18th August 2018, 17:36 Go to last post

  5. Neural network implementation using VLSI

    Started by Udit_agarwal, 15th August 2018 18:25
    • Replies: 1
    • Views: 173
    nmag
    18th August 2018, 02:06 Go to last post

  6. How to sweep Threshold Voltage using .pm model file?

    Started by npsnpsnps, 17th August 2018 13:29
    • Replies: 0
    • Views: 130
    npsnpsnps
    17th August 2018, 13:29 Go to last post

  7. Resistor Layout - Unit Cell Selection

    Started by Puppet123, 14th August 2018 17:29
    • Replies: 3
    • Views: 186
    rangermad
    17th August 2018, 13:29 Go to last post

  8. Building a solar cell 18650 battery charger + a voltage output circuit

    Started by adwnis123, 15th August 2018 21:58
    • Replies: 2
    • Views: 251
    BradtheRad
    17th August 2018, 04:12 Go to last post

  9. Mixed IC Design Flow Using: Synopsys DC-ICC & Cadence Virtuoso

    Started by ryu_hayabusa, 17th August 2018 03:37
    • Replies: 0
    • Views: 63
    ryu_hayabusa
    17th August 2018, 03:37 Go to last post

  10. Problem with plotting bathtub curve in ads

    Started by ultrasonic.1991, 14th August 2018 21:35
    2 Attachment(s)
    • Replies: 0
    • Views: 137
    ultrasonic.1991
    14th August 2018, 21:35 Go to last post

  11. questions about eye diagram of transimpedance amplifier

    Started by ultrasonic.1991, 1st August 2018 12:33
    11 Attachment(s)
    • Replies: 14
    • Views: 730
    KlausST
    14th August 2018, 07:36 Go to last post

  12. Layout of complementary clock signal trace

    Started by AllenD, 13th August 2018 05:54
    • Replies: 1
    • Views: 170
    cariban
    13th August 2018, 09:31 Go to last post

  13. Two stage operational amplifier

    Started by Green_Ic, 12th August 2018 12:57
    1 Attachment(s)
    • Replies: 2
    • Views: 181
    dick_freebird
    12th August 2018, 18:59 Go to last post

  14. SKILL Language: Meaning of "Hi"

    Started by XDJ_HBT, 11th August 2018 17:07
    • Replies: 2
    • Views: 260
    XDJ_HBT
    12th August 2018, 13:38 Go to last post

  15. TSMC 65nm Pad Issues

    Started by Puppet123, 11th August 2018 00:15
    • Replies: 0
    • Views: 169
    Puppet123
    11th August 2018, 00:15 Go to last post

  16. Virtuoso ADEXL Calculator Question

    Started by ljp2706, 8th August 2018 20:42
    • Replies: 1
    • Views: 196
    Dominik Przyborowski
    9th August 2018, 20:02 Go to last post

  17. Top level IO cells connection (multiple IO voltages and global source use) and ESD

    Started by NikosTS, 3rd August 2018 14:57
    2 Pages •
    1 2
    6 Attachment(s)
    • Replies: 22
    • Views: 699
    dick_freebird
    8th August 2018, 22:48 Go to last post

  18. Mosfet working in sub-threshold region

    Started by AllenD, 29th July 2018 07:14
    • Replies: 4
    • Views: 315
    dr_kca
    8th August 2018, 12:41 Go to last post

  19. PEX LVS ERROR: Ground Net not defined

    Started by s_babayan, 7th August 2018 13:56
    • Replies: 1
    • Views: 93
    dr_kca
    8th August 2018, 12:22 Go to last post

  20. [SOLVED] What's the difference between stacked and cascode configurations?

    Started by Fávero Santos, 18th July 2018 00:12
    1 Attachment(s)
    • Replies: 2
    • Views: 260
    khaled2k
    8th August 2018, 12:11 Go to last post

  21. How to optimize all transistors' size (length and width) in Cadence software?

    Started by Chaoping, 3rd August 2018 03:45
    • Replies: 4
    • Views: 228
    khaled2k
    8th August 2018, 11:57 Go to last post

  22. Reliability question for a casode 3.3V buffer using 1.8V MOS.

    Started by dr_kca, 6th August 2018 15:14
    1 Attachment(s)
    • Replies: 3
    • Views: 184
    khaled2k
    8th August 2018, 11:53 Go to last post

  23. TSMC 0.18um CMOS Tech - Question on Maturity

    Started by rmanalo, 8th August 2018 09:57
    • Replies: 1
    • Views: 98
    khaled2k
    8th August 2018, 10:02 Go to last post

  24. I want to learn FPGA board design

    Started by ali_umair21, 7th August 2018 18:45
    • Replies: 4
    • Views: 182
    KlausST
    8th August 2018, 06:37 Go to last post

  25. Importing Files from ASITIC (CIF files) Into Cadence

    Started by Puppet123, 4th August 2018 01:15
    1 Attachment(s)
    • Replies: 3
    • Views: 345
    Puppet123
    7th August 2018, 23:07 Go to last post

  26. L-edit technology file

    Started by yashfaith, 7th August 2018 16:37
    1 Attachment(s)
    • Replies: 0
    • Views: 86
    yashfaith
    7th August 2018, 16:37 Go to last post

  27. question about input impedance of transimpedance amplifier

    Started by ultrasonic.1991, 7th August 2018 14:50
    • Replies: 1
    • Views: 103
    pancho_hideboo
    7th August 2018, 15:33 Go to last post

  28. Boost regulator for 3.6V

    Started by Kick, 6th August 2018 07:39
    1 Attachment(s)
    • Replies: 3
    • Views: 160
    Kick
    7th August 2018, 06:19 Go to last post

  29. Cadence virtuoso CDB to OA conversion ( schematic view problem )

    Started by NikosTS, 6th August 2018 10:30
    • Replies: 0
    • Views: 101
    NikosTS
    6th August 2018, 10:30 Go to last post

  30. Layout of Differential Opamp

    Started by Puppet123, 5th May 2018 05:58
    4 Attachment(s)
    • Replies: 10
    • Views: 1,060
    erikl
    5th August 2018, 17:11 Go to last post
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