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Threads 1 to 30 of 18958

Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 590
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 28,462
    klug
    3rd December 2007, 18:00 Go to last post

  1. Finding Q of Pie matching network

    Started by Chinmaye, Yesterday 18:09
    • Replies: 0
    • Views: 59
    Chinmaye
    Yesterday, 18:09 Go to last post

  2. UHF RFID Chip impedance with 50 ohm

    Started by shanmei, 19th January 2019 21:23
    • Replies: 0
    • Views: 171
    shanmei
    19th January 2019, 21:23 Go to last post

  3. LFoundry layout design rules

    Started by student14, 19th January 2019 18:57
    1 Attachment(s)
    • Replies: 0
    • Views: 90
    student14
    19th January 2019, 18:57 Go to last post

  4. The confinement effect in thin(and small width) metal tracks?

    Started by melkord, 7th January 2019 08:18
    • Replies: 3
    • Views: 334
    timof
    18th January 2019, 09:32 Go to last post

  5. How to run .scs netlist file cadence

    Started by npsnpsnps, 16th January 2019 18:55
    • Replies: 6
    • Views: 249
    npsnpsnps
    18th January 2019, 01:31 Go to last post

  6. ESD and parasitic inductances of bond wire

    Started by ICnow, 15th January 2019 15:48
    • Replies: 3
    • Views: 229
    dick_freebird
    17th January 2019, 19:40 Go to last post

  7. SAR logic design for 10-bit SAR ADC ?

    Started by Electric_Shock, 17th January 2019 15:06
    2 Attachment(s)
    • Replies: 0
    • Views: 108
    Electric_Shock
    17th January 2019, 15:06 Go to last post

  8. instrumentation amplifier with wide differential input

    Started by Junus2012, 12th January 2019 21:09
    • Replies: 3
    • Views: 253
    LvW
    14th January 2019, 17:06 Go to last post

  9. Voltage to current converter of high speed CDR circuit

    Started by usuikazkou, 11th January 2019 08:19
    6 Attachment(s)
    • Replies: 4
    • Views: 382
    frankrose
    11th January 2019, 19:35 Go to last post

  10. Source code of skill function of Cadence Virtuoso

    Started by quyleanh, 10th January 2019 01:18
    • Replies: 3
    • Views: 241
    quyleanh
    11th January 2019, 05:31 Go to last post

  11. Perl/Python Scripting for Analog/Mixed Signal Design

    Started by Puppet123, 9th January 2019 21:09
    • Replies: 2
    • Views: 268
    dpaul
    10th January 2019, 10:08 Go to last post

  12. DAC design for 14- bit SAR ADC

    Started by ajaychowdharykr, 6th January 2019 13:22
    • Replies: 3
    • Views: 296
    dick_freebird
    7th January 2019, 19:07 Go to last post

  13. Missing via (M1-substrate)&(M1-nwell) bulk tsmc65N

    Started by bll_hb, 4th January 2019 13:46
    • Replies: 1
    • Views: 224
    dick_freebird
    4th January 2019, 23:44 Go to last post

  14. 28nm and Below MOS Layout

    Started by Puppet123, 3rd January 2019 02:20
    • Replies: 0
    • Views: 326
    Puppet123
    3rd January 2019, 02:20 Go to last post

  15. Inter-digitization Pattern and Dummies for MOS Layout

    Started by Puppet123, 22nd December 2018 22:49
    • Replies: 2
    • Views: 251
    rangermad
    2nd January 2019, 13:28 Go to last post

  16. N-well antenna effect

    Started by saha.123, 24th December 2018 17:30
    • Replies: 3
    • Views: 228
    rangermad
    2nd January 2019, 13:26 Go to last post

  17. Analog Layout Finger Size

    Started by Puppet123, 22nd December 2018 22:35
    • Replies: 4
    • Views: 487
    dick_freebird
    30th December 2018, 02:14 Go to last post

  18. What is ref layer (stream number : datatype 0:0) in mosaic instance

    Started by quyleanh, 26th December 2018 06:00
    • Replies: 0
    • Views: 236
    quyleanh
    26th December 2018, 06:00 Go to last post

  19. Exclusion Layers for Dummy Metal Fill

    Started by Puppet123, 22nd December 2018 21:38
    • Replies: 3
    • Views: 244
    quyleanh
    26th December 2018, 02:14 Go to last post

  20. Coupling capacitance between clock signal and voltage signal.

    Started by saha.123, 24th December 2018 17:37
    • Replies: 1
    • Views: 207
    dick_freebird
    24th December 2018, 21:35 Go to last post

  21. Switched Capacitor Circuits - PSS/PAC

    Started by Puppet123, 1st September 2018 00:36
    • Replies: 14
    • Views: 1,645
    pancho_hideboo
    21st December 2018, 09:48 Go to last post

  22. Analog Layout and Dummies

    Started by Puppet123, 20th December 2018 21:18
    • Replies: 2
    • Views: 252
    dick_freebird
    21st December 2018, 01:03 Go to last post

  23. bit pattern generator in Cadence Virtuoso

    Started by morfozar, 20th December 2018 16:43
    • Replies: 1
    • Views: 199
    dick_freebird
    20th December 2018, 20:35 Go to last post

  24. degeneration differential pair

    Started by Junus2012, 17th December 2018 00:34
    1 Attachment(s)
    • Replies: 9
    • Views: 572
    erikl
    17th December 2018, 22:37 Go to last post

  25. complementary input folded cascode opam

    Started by Junus2012, 6th December 2018 18:08
    2 Attachment(s)
    • Replies: 12
    • Views: 850
    erikl
    17th December 2018, 22:13 Go to last post

  26. Paper showing intrinsic gain vs. minimum channel length evolution?

    Started by spectrallypure, 17th December 2018 13:08
    1 Attachment(s)
    • Replies: 1
    • Views: 182
    dick_freebird
    17th December 2018, 18:54 Go to last post

  27. How to get a TSMC 65nm 10M Ohm Resistor

    Started by EEPuppyPuppy, 14th December 2018 19:42
    • Replies: 1
    • Views: 266
    dick_freebird
    14th December 2018, 22:21 Go to last post

  28. Trimming offset voltage

    Started by zhorik21, 12th December 2018 14:59
    1 Attachment(s)
    • Replies: 3
    • Views: 289
    frankrose
    13th December 2018, 15:03 Go to last post

  29. Difference between single flat cell check and hierarchical layout (hcell) check

    Started by quyleanh, 29th November 2018 08:16
    • Replies: 5
    • Views: 529
    rangermad
    13th December 2018, 12:21 Go to last post

  30. When was Cadence Maestro introduced into Cadence Virtuoso ?

    Started by Puppet123, 11th December 2018 05:31
    • Replies: 1
    • Views: 212
    pancho_hideboo
    11th December 2018, 07:45 Go to last post
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