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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 1,207
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 29,106
    klug
    3rd December 2007, 18:00 Go to last post

  1. Offset nonlinearity of Rail-to-Rail OpAmp

    Started by ICnow, Today 14:36
    • Replies: 0
    • Views: 1
    ICnow
    Today, 14:36 Go to last post

  2. Deaign of low ON resistor CMOS transmission gate

    Started by Junus2012, 17th April 2019 12:26
    1 Attachment(s)
    • Replies: 8
    • Views: 324
    rmanalo
    Today, 14:35 Go to last post

  3. Worst case Corner Analyses in Cadence

    Started by Junus2012, 10th April 2019 11:33
    2 Pages •
    1 2
    2 Attachment(s)
    • Replies: 20
    • Views: 1,569
    Junus2012
    Today, 13:39 Go to last post

  4. Difference between 180nm and 130nm with same W/L ratio

    Started by jaydnul, 17th April 2019 23:31
    • Replies: 3
    • Views: 171
    dick_freebird
    Yesterday, 22:12 Go to last post

  5. [SOLVED] Signal Ground attached to my DC bias ground?

    Started by Hawaslsh, 16th April 2019 00:09
    9 Attachment(s)
    • Replies: 15
    • Views: 311
    KlausST
    Yesterday, 16:08 Go to last post

  6. Resources to learn about silicon photonics IC design

    Started by RamyRady_RF, 17th April 2019 12:48
    • Replies: 0
    • Views: 65
    RamyRady_RF
    17th April 2019, 12:48 Go to last post

  7. Input common mode range simulation for fully differential amplifier

    Started by Junus2012, 2nd April 2019 11:20
    1 Attachment(s)
    • Replies: 7
    • Views: 644
    Junus2012
    16th April 2019, 22:23 Go to last post

  8. [SOLVED] Frequency compensation using Null resistor

    Started by Robotduck, 16th April 2019 19:49
    1 Attachment(s)
    • Replies: 1
    • Views: 118
    vivekroy
    16th April 2019, 21:18 Go to last post

  9. Zero diagonal found in Jacobian error in simulation the DAC?

    Started by Electric_Shock, 16th April 2019 07:17
    2 Attachment(s)
    • Replies: 2
    • Views: 128
    dick_freebird
    16th April 2019, 20:49 Go to last post

  10. [SOLVED] Power Supply Rejection Ratio

    Started by Robotduck, 16th April 2019 16:08
    • Replies: 1
    • Views: 153
    KlausST
    16th April 2019, 16:27 Go to last post

  11. Create a long delay with using inverter gate?

    Started by Electric_Shock, 10th April 2019 13:13
    1 Attachment(s)
    • Replies: 10
    • Views: 340
    sutapanaki
    14th April 2019, 21:25 Go to last post

  12. Simulating Mos varctor

    Started by Gurjar, 13th April 2019 11:11
    • Replies: 1
    • Views: 122
    frankrose
    14th April 2019, 09:41 Go to last post

  13. MOSFET diode connected for biasing

    Started by Junus2012, 4th April 2019 16:59
    5 Attachment(s)
    • Replies: 9
    • Views: 1,017
    Junus2012
    13th April 2019, 13:59 Go to last post

  14. UHF RFID Chip impedance with 50 ohm

    Started by shanmei, 19th January 2019 21:23
    • Replies: 9
    • Views: 946
    vivekroy
    13th April 2019, 11:05 Go to last post

  15. Verilog-A $Strobe statement display in virtuoso

    Started by MahmoudHassan, 10th April 2019 17:55
    1 Attachment(s)
    • Replies: 1
    • Views: 125
    pancho_hideboo
    11th April 2019, 05:43 Go to last post

  16. Help in Verilog-A with cadence virtuoso

    Started by MahmoudHassan, 5th April 2019 17:58
    1 Attachment(s)
    • Replies: 10
    • Views: 765
    pancho_hideboo
    11th April 2019, 05:27 Go to last post

  17. [moved] ZnO solution/Drop casting

    Started by Melina2018, 10th April 2019 06:59
    • Replies: 0
    • Views: 92
    Melina2018
    10th April 2019, 06:59 Go to last post

  18. LVS failed issue - Cannot Find Switch Cells...

    Started by jylei, 9th April 2019 22:54
    • Replies: 0
    • Views: 121
    jylei
    9th April 2019, 22:54 Go to last post

  19. Monticarlo Analyses in Cadence

    Started by Junus2012, 6th April 2019 23:29
    2 Pages •
    1 2
    3 Attachment(s)
    • Replies: 22
    • Views: 2,309
    Junus2012
    9th April 2019, 19:07 Go to last post

  20. How to find formula of calculating resistance in Pcell?

    Started by quyleanh, 9th April 2019 13:35
    • Replies: 2
    • Views: 129
    Dominik Przyborowski
    9th April 2019, 18:23 Go to last post

  21. Post layout simulation results differ from prelayout simulation- S21 is negative

    Started by sp.bhuvana, 2nd April 2019 05:59
    2 Attachment(s)
    • Replies: 7
    • Views: 768
    sp.bhuvana
    9th April 2019, 10:41 Go to last post

  22. Effect of Gds on Gain

    Started by shruthi08, 20th March 2019 17:14
    4 Attachment(s)
    • Replies: 12
    • Views: 1,833
    sutapanaki
    9th April 2019, 07:00 Go to last post

  23. Layout related issues: ground scheme, bias current

    Started by AllenD, 7th April 2019 07:59
    • Replies: 2
    • Views: 328
    vivekroy
    7th April 2019, 13:54 Go to last post

  24. AC / Noise after a tran

    Started by Fabien, 5th April 2019 10:28
    • Replies: 3
    • Views: 226
    FvM
    7th April 2019, 08:46 Go to last post

  25. Verilog-A platform for windows

    Started by MahmoudHassan, 5th April 2019 17:51
    • Replies: 1
    • Views: 180
    pancho_hideboo
    6th April 2019, 16:57 Go to last post

  26. Current in bulk cascode device

    Started by maxporter, 4th April 2019 16:07
    1 Attachment(s)
    • Replies: 2
    • Views: 190
    maxporter
    4th April 2019, 22:18 Go to last post

  27. [SOLVED] Accurate transient setting for DFT and Spectrum in cadence

    Started by Junus2012, 1st April 2019 16:07
    5 Attachment(s)
    • Replies: 15
    • Views: 1,781
    Junus2012
    3rd April 2019, 21:08 Go to last post

  28. What does it mean to check mismatch and process in ADEXL Monte Carlo?

    Started by Megahed89, 2nd April 2019 22:46
    • Replies: 2
    • Views: 155
    vivekroy
    3rd April 2019, 12:40 Go to last post

  29. RFESDpads use instead of I/O pads

    Started by student14, 3rd April 2019 08:34
    • Replies: 0
    • Views: 81
    student14
    3rd April 2019, 08:34 Go to last post

  30. gm of this feedback common source transistor

    Started by shanmei, 30th March 2019 16:28
    2 Attachment(s)
    • Replies: 5
    • Views: 641
    shanmei
    2nd April 2019, 16:58 Go to last post
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