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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 2,711
    B. David Miyares
    1st May 2018, 14:19 Go to last post

  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 30,252
    klug
    3rd December 2007, 18:00 Go to last post

  1. Rplpoly layout matching problem

    Started by agarwalneeraj1, Yesterday 08:08
    • Replies: 4
    • Views: 151
    frankrose
    Today, 18:57 Go to last post

  2. resistor mismatch and the resolution

    Started by shanmei, 19th September 2019 20:20
    • Replies: 1
    • Views: 189
    std_match
    19th September 2019, 23:24 Go to last post

  3. deviding Y value by X values in Cadence Virtuoso calculator

    Started by Junus2012, 17th September 2019 16:29
    6 Attachment(s)
    • Replies: 9
    • Views: 302
    pancho_hideboo
    19th September 2019, 14:40 Go to last post

  4. Error in AMS simulation.

    Started by Chinmaye, 19th September 2019 14:08
    • Replies: 0
    • Views: 90
    Chinmaye
    19th September 2019, 14:08 Go to last post

  5. Converting verilog code into a symbol during AMS simulation

    Started by Chinmaye, 17th September 2019 08:40
    • Replies: 5
    • Views: 178
    Chinmaye
    19th September 2019, 14:00 Go to last post

  6. Operational amplifier driving capability test

    Started by Junus2012, 17th September 2019 16:00
    3 Attachment(s)
    • Replies: 11
    • Views: 272
    dick_freebird
    19th September 2019, 04:20 Go to last post

  7. Common mode gain simulation for differential amplifier using balun

    Started by Junus2012, 18th September 2019 09:58
    1 Attachment(s)
    • Replies: 0
    • Views: 143
    Junus2012
    18th September 2019, 09:58 Go to last post

  8. Physical Verification with TSMC65nm CRN65LP PDK

    Started by Puppet123, 18th September 2019 04:14
    • Replies: 1
    • Views: 123
    Puppet123
    18th September 2019, 06:58 Go to last post

  9. Differential and common mode input resistance of the fully diffferential amplifier

    Started by Junus2012, 2nd September 2019 13:17
    2 Pages •
    1 2
    8 Attachment(s)
    • Replies: 22
    • Views: 920
    Junus2012
    17th September 2019, 09:55 Go to last post

  10. Level Shifters: Trends in Delay and Transition Time

    Started by janthonym, 16th September 2019 23:22
    • Replies: 1
    • Views: 172
    BradtheRad
    17th September 2019, 08:21 Go to last post

  11. What is the difference between LVS and ERC ?

    Started by MubarakKhan, 13th September 2019 11:36
    • Replies: 2
    • Views: 197
    timof
    17th September 2019, 03:55 Go to last post

  12. Analog 16:1 MUX IC question, 4 vs 1 stage, transmission gate vs nmos

    Started by OG_, 16th September 2019 18:06
    2 Attachment(s)
    • Replies: 1
    • Views: 120
    dick_freebird
    17th September 2019, 02:05 Go to last post

  13. [SOLVED] AMS simulation of D-FF

    Started by Chinmaye, 16th September 2019 12:30
    1 Attachment(s)
    • Replies: 2
    • Views: 165
    dick_freebird
    16th September 2019, 18:19 Go to last post

  14. ConnectLib files in ams simulation Cadence

    Started by Chinmaye, 15th September 2019 19:19
    • Replies: 0
    • Views: 122
    Chinmaye
    15th September 2019, 19:19 Go to last post

  15. Combine circuit and Verilog in Cadence

    Started by Chinmaye, 14th September 2019 18:09
    • Replies: 1
    • Views: 197
    Dominik Przyborowski
    14th September 2019, 18:30 Go to last post

  16. Problems in Verifying Silterra Library Cells using Calibre

    Started by JLHW, 13th September 2019 17:12
    1 Attachment(s)
    • Replies: 0
    • Views: 107
    JLHW
    13th September 2019, 17:12 Go to last post

  17. Verilog-a code to latch analog voltages

    Started by Chinmaye, 11th September 2019 07:11
    1 Attachment(s)
    • Replies: 7
    • Views: 333
    vivekroy
    12th September 2019, 19:51 Go to last post

  18. DNL/INL Measurement in Cadence for DAC

    Started by Puppet123, 12th September 2019 01:45
    • Replies: 2
    • Views: 229
    Dominik Przyborowski
    12th September 2019, 04:44 Go to last post

  19. INL/DNL Measurement from Cadence Spectre/Virtuoso Output

    Started by Puppet123, 6th September 2019 21:44
    • Replies: 7
    • Views: 444
    pancho_hideboo
    12th September 2019, 01:32 Go to last post

  20. Verilog-a code for differential amplifier

    Started by Chinmaye, 11th September 2019 07:20
    • Replies: 4
    • Views: 227
    Chinmaye
    11th September 2019, 18:49 Go to last post

  21. Current reference design for CS-DAC

    Started by Shishira, 6th September 2019 19:07
    1 Attachment(s)
    • Replies: 5
    • Views: 322
    Dominik Przyborowski
    11th September 2019, 06:07 Go to last post

  22. How to change the m factor (multiplication factor) for Instances in cadence

    Started by Junus2012, 26th August 2019 19:31
    1 Attachment(s)
    • Replies: 5
    • Views: 298
    Dominik Przyborowski
    10th September 2019, 20:12 Go to last post

  23. Charge pump topology

    Started by bharath_k, 5th September 2019 11:44
    2 Attachment(s)
    • Replies: 4
    • Views: 583
    bharath_k
    9th September 2019, 09:42 Go to last post

  24. ADE-XL: 2 tests have a same variable but it is constant for test1 and swept for tes2

    Started by circuitking, 9th September 2019 01:56
    • Replies: 1
    • Views: 180
    Dominik Przyborowski
    9th September 2019, 04:46 Go to last post

  25. W/L of pMOS and nMOS of CD4007 Chip.

    Started by vijender13, 6th September 2019 06:20
    • Replies: 3
    • Views: 243
    frankrose
    8th September 2019, 22:24 Go to last post

  26. Generate pulses of different widths

    Started by Chinmaye, 8th September 2019 10:20
    • Replies: 1
    • Views: 152
    erikl
    8th September 2019, 20:21 Go to last post

  27. Error and Questions related to Calibre 2015 in Cadence

    Started by JLHW, 8th September 2019 18:22
    2 Attachment(s)
    • Replies: 0
    • Views: 144
    JLHW
    8th September 2019, 18:22 Go to last post

  28. Changing the 'VSS' value in CppSim

    Started by vivekroy, 8th September 2019 14:04
    • Replies: 0
    • Views: 140
    vivekroy
    8th September 2019, 14:04 Go to last post

  29. Help on Ocean scripting: run one analysis and use that results in another

    Started by circuitking, 6th September 2019 21:59
    • Replies: 8
    • Views: 409
    vivekroy
    8th September 2019, 13:37 Go to last post

  30. Factors deciding Silicon Wafer Thickness

    Started by Vishu21_95, 29th August 2019 06:53
    • Replies: 2
    • Views: 240
    dick_freebird
    5th September 2019, 02:22 Go to last post
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