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Recent content by seanwu

  1. S

    Several questions about STA

    reg2reg hold violations You can not reduce skew to zero since there is on-chip variation.
  2. S

    Pull-up resistors's problem

    I dont agree with the issue. Probably it is true in special case.
  3. S

    When will the hold time violations occur?

    hold time violations Hold time violation i.e. min. time violation, means that data input signal to a storage element(eg. F.F.) changs too quickly before the value of input signal be safely stored in it.
  4. S

    SDRAM interconnection test

    SDRAMs currently not suport boundary scan. You can use the FPGA to access the DRAMs. Anywhere, you can use a logic analyizer to debug the DRAM sub-system.
  5. S

    protocol reset should be treat as syn reset or asyn reset?

    You'd better treat protocol reset as asyn. reset. Performing syn. reset requires additional condition, it means, you may violate the protocol.
  6. S

    Perl, Regular expression?

    Hi Davy, try the following. /[\d\w ]\/[\d\w ]/
  7. S

    Verilog doubt - sequential logic

    verilog doubt What is your mean? NO syntax error in the code.
  8. S

    double clock feed to synchronous state machine

    double clocking Asynchoronous signal does.
  9. S

    Problem with synthesized RTL code

    Problem of synthesis You can set_dont_use on negedge F.F. cells to resolve the problem. You had better to create_clock on hpixvalidclk_mux before compile.
  10. S

    MOS smaller than the contact head for tsmc 0.18

    tsmc018 You can widen and extend the poly to surround the contact without changing the mos.
  11. S

    Can memory arbiter be realized with combinational logic?

    Memory arbiter Compared with nomal arbiter, what is special for memory arbiter ?
  12. S

    What's the difference between STA and GLS?

    STA vs GLS You can skip gate level simulation when you have enough confidence.
  13. S

    insert scan chain problem

    I'd rather insert scan chain after all cells be placed.
  14. S

    What is retiming in STA and where to use it?

    Retiming Today, synthesis tool can perform retiming, but I still not heared of retiming during STA.
  15. S

    problem about dc writing out

    Can you show me the hierarchy of your modules?
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