Verilog doubt - sequential logic

[pravi]

verilog doubt

else
begin
previous<={previous[1:0],data};
seqfound<={previous==pattern_searched_for};
end

 

[seanwu]

verilog doubt

What is your mean? NO syntax error in the code.

 

[jnanabindu]

Re: verilog doubt

I think you are refering to the delay involved in generation of seqfound signal.

previous<={previous[1:0],data};
seqfound<={previous==pattern_searched_for};

When you change the value of previous signal, this value is available to seqfound expression in the next iteration of the flow. This is because you have declared the previous signal as reg. Try declaring it as wire. Hope that will solve your problem.

 

[zhangpengyu]

verilog doubt

It's maybe for sequence detection.
The register previous is to store input streem.

 

[s8319]

Re: verilog doubt

I think you are refering to the delay involved in generation of seqfound signal.

previous<={previous[1:0],data};
seqfound<={previous==pattern_searched_for};

When you change the value of previous signal, this value is available to seqfound expression in the next iteration of the flow. This is because you have declared the previous signal as reg. Try declaring it as wire. Hope that will solve your problem.

As the non blocking assignments are used, the circuit should be a sequential logic, triggered by clock, so the changement in previous signal is available in next cycle.
If you want to describe a combitional logic, using blocking assignments, change the sensitive signals of the block.

previous =previous[1:0],data};
seqfound={previous==pattern_searched_for};

maybe

 

[amraldo]

Re: verilog doubt

I think this is a sequence detector. The given code uses value of previous from the previous itteration in the current iteration loop. This leads to simulation mismatch before & after synthesis. Using the "=" is a solution but it is not recommended in HDL design. It is always better to use the "<=" if possible.
I think a better solution is to move the statement :

seqfound<={previous==pattern_searched_for};

outside the sequential statement context to a concuurent statement context.
Another good hint is to assign any variable within 1 & only one concurrent statement.
Regards,
Amraldo.