Problem with synthesized RTL code

[alpacinoliu]

RTL code is synthesized to use DC(version: 2003.12-SP1 for LinuX). As a result, synthesized netlist is not what I expected( as figure 1), as its function is right. I want to get schematic as figue 2. How to get the schematic as figure 2? Any advice and discussion is expected and appreciated.
Thand you in advance
RTL code as follow:

assign lbswaprstz = hwresetz & (scan_testmode | ~vpixvalidrp);
always @(posedge hpixvalidclk_mux or negedge lbswaprstz)
begin
  if (!lbswaprstz) begin
	lb2wsel <= 0;
	lb3wsel <= 0;
                lb4wsel <= 0;
                lb5wsel <= 0;
  end else begin
	lb2wsel <= lb1wsel;
	lb3wsel <= lb2wsel;
                lb4wsel <= lb3wsel;
                lb5wsel <= lb4wsel;
  end
end

assign  lbswaprst1z = (scan_testmode) ? hwresetz : lbswaprstz | ~shiften;
assign   lbswaprst2z = (scan_testmode) ? hwresetz : lbswaprstz | shiften;
always @(posedge hpixvalidclk_mux or negedge lbswaprst1z or negedge lbswaprst2z)
begin
  if (!lbswaprst1z) begin
	lb0wsel <= 0;
	lb1wsel <= 1;
  end else if (!lbswaprst2z) begin
	lb0wsel <= 1;
	lb1wsel <= 0;
  end else begin
                lb0wsel <= lb5wsel;    
                lb1wsel <= lb0wsel;
  end
end

 

[ami]

Re: Problem of synthesis

try this in your DC script
1. first, create_clock for hpixvalidclk_mux
2. then set_dont_touch_network for the clock & reset signals (lbswaprstz,lbswaprst1z, lbswaprst2z)
Hope this help!
AMi

 

[alpacinoliu]

Re: Problem of synthesis

try this in your DC script
1. first,
2. then set_dont_touch_network for the clock & reset signals (lbswaprstz,lbswaprst1z, lbswaprst2z)
Hope this help!
AMi

i have already done what you refer, but problem above still exists .
Thanks for your reply

 

[anjali]

Re: Problem of synthesis

what are the drivers of n17 & n18?

 

[ami]

Re: Problem of synthesis

1. use scan_mux for scan_test signal and set_dont_touch_attribute for those scan_mux
2. set_dont_touch network for all clock & reset signal

 

[ami]

Re: Problem of synthesis

Multiplexer Inference for a Specific case Statement

module mux8to1 (DIN, SEL, DOUT);
input [7:0] DIN;
input [2:0] SEL;
output DOUT;
reg DOUT;
always@(SEL or DIN)
begin: blk1
case (SEL) // synopsys infer_mux
3’b000: DOUT <= DIN[0];
3’b001: DOUT <= DIN[1];
3’b010: DOUT <= DIN[2];
3’b011: DOUT <= DIN[3];
3’b100: DOUT <= DIN[4];
3’b101: DOUT <= DIN[5];
3’b110: DOUT <= DIN[6];
3’b111: DOUT <= DIN[7];
endcase
end
endmodule

 

[seanwu]

Problem of synthesis

You can set_dont_use on negedge F.F. cells to resolve the problem.
You had better to create_clock on hpixvalidclk_mux before compile.

 

[alpacinoliu]

Re: Problem of synthesis

Multiplexer Inference for a Specific case Statement

module mux8to1 (DIN, SEL, DOUT);
input [7] DIN;
input [2] SEL;
output DOUT;
reg DOUT;
always@(SEL or DIN)
begin: blk1
case (SEL) // synopsys infer_mux
3’b000: DOUT <= DIN[0];
3’b001: DOUT <= DIN[1];
3’b010: DOUT <= DIN[2];
3’b011: DOUT <= DIN[3];
3’b100: DOUT <= DIN[4];
3’b101: DOUT <= DIN[5];
3’b110: DOUT <= DIN[6];
3’b111: DOUT <= DIN[7];
endcase
end
endmodule

I don't understand what you mean ?

Added after 8 minutes:

You can set_dont_use on negedge F.F. cells to resolve the problem.
You had better to create_clock on hpixvalidclk_mux before compile.

thank you !

1. yes! set_dont_use on negedge F.F.cell can meet this problem, but I dont want to use this command , because DFFNs are used in synthesizing other modules.

Now I have firstly to synthesize this module alone by use "set_dont_use", and then read the netlist of this module into and link the design totally.

thanks for all reply!