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Depending on your education background, if you know much about device physics, analog is a good and popular field to enter now; however, if you know only digital logic and have basic programming skills, you can take digital design and verification for choice.
Regards,
RP,
I think the best qualification is simply your hand-on working experience, and the complexity of the projects you have ever involved, and your roles in the projects.
If you don't have hand-on experience, most companies may ask for better educational background, say if you are graduated from a...
layout in verilog
I dont know why you want to generate a layout from spice netlist. The normal
design flow for an analog design or for a full custom design should be roughly
as follows:
1) design the logic/circuit for your project.
1) draw the layout, using Candence tool or other comercial...
I have been both an ASIC designer and a verification engineer. I heared more
than one times, that smart guys are selected as designers, while newbies and
guys who are not so smart, are chosen as verification engineers. Is that true?
What do you guys think about it, and which position is paid...
Re: vera Versus specman
As a TOP 5 semiconductor company, we use e for several years, it seems a very successful approach to mix e based verification with the traditional HDL based directed tests. However, we are also developing apporaches fully based on e.
E is powerful because its ability to...
statement branch condition
Hi,
What is the code context? Is it intended to be in a combinational block, or
in a sequential block?
It should be ok if you put reg_a <= ~reg_a in a sequential block, with
posedge or negedge of clock as your sensitivity list events. But you cannot
do something...
SOC functional verification is a big topic, and a difficult task as well.
First of all, you need a test/verification plan, and build your verification environment based on your plan, using HDL and c/c++(traditionally),
or using e (the state of the art technique). After you built your...
Re: What's the IC designer's future? Always designing or oth
In an IC designer's career, he may need to learn more than 3 languages, C/C++,
VHDL/Verilog/system_verilog, and couple of other EDA tools/languages, that very much limited a designer to expoit more his/her capability in other fields...
Re: q of verification?
1) Create verification plan
2) Create testbench, using HDL or e.
3) Create testcases.
4) Run simulation.
5) Check results and coverage.
Regards,
best free vhdl editor
It very much depends on your working environment. As far as I am
concerned, I am using Unix VI, and I am very happy with it.
Emacs is also a good choice.
Most of the times, it is because of the timing issues, say, you are drving a net
with a big distributed RC, you may need some cascaded buffers. Some times,
it is because of logic reasons, say, you are implementing an AND logic, you may
need a NAND and an inverter.
Regards,
verilog `define fsm
You cannot do the same thing in Verilog as far as I know.
However, you can define the state coding using parameter statement.
Regards,
Re: about verification
I don't know much about system-verilog, but it seems that system-verilog adopted
many features from C and verilog. Suppose system-verilog has also adopted many features from vera and e, it should be very powerful, but very difficult to learn (e is difficult to learn too)...
Re: system-c
It is said systemC will find widely applications in few years, because it can be
used to model the whole system, and because its strong support to hw/sw
co-verification. Seems, it has been used already in EU and JP.
HDL's (Verilog and VHDL) are mainly used for RTL design now...
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