cevitamic
Newbie level 6
verilog fsm parameter
In VHDL, the states of a FSM can be defined as enumerate types, so that in ModelSim, literate state names can be shown. How can I do the similar thing in Verilog HDL?
In VHDL, the states of a FSM can be defined as enumerate types, so that in ModelSim, literate state names can be shown. How can I do the similar thing in Verilog HDL?