iamczx
Member level 3
branch condition impossible to meet)
When I read_verilog , this warning come out. And a strange things happend when I check my code:
there is a case sentence in the code:
case(current_state):
`IDLE:
.....
......
`READ:
begin
wr<= ~wr; //here is the probem
........
end
.......
endcase
if i comment the wr <= ~ wr; or change it to: wr <= constant;(such as 1'b1);
the warning will disappear!
but ,why ?? The `READ branch is arrivable in fact, and why it becomes unreachable when the sentence " wr <= ~wr;" exist.
Anyone can tell me why? Thanks in advance.
When I read_verilog , this warning come out. And a strange things happend when I check my code:
there is a case sentence in the code:
case(current_state):
`IDLE:
.....
......
`READ:
begin
wr<= ~wr; //here is the probem
........
end
.......
endcase
if i comment the wr <= ~ wr; or change it to: wr <= constant;(such as 1'b1);
the warning will disappear!
but ,why ?? The `READ branch is arrivable in fact, and why it becomes unreachable when the sentence " wr <= ~wr;" exist.
Anyone can tell me why? Thanks in advance.