Undefined output values with synthesized netlist

[bongosontan]

Hello everyone,

This might be a stupid question but my brain is not braining so this might be a very trivial problem that I can not figure out myself at this moment. Here we go:

I am trying to design a simple frequency divider circuit in verilog :

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
`timescale 1ns / 1ps
module Clock_divider(reset, clk40, clock_out_2, clock_out_5, clock_out_10);
input reset;
input clk40;
output reg clock_out_2;
output reg clock_out_5;
output reg clock_out_10;
reg[27:0] counter_2=28'd0;
reg[27:0] counter_5=28'd0;
reg[27:0] counter_10=28'd0;
parameter DIVISOR_2 = 28'd2;
parameter DIVISOR_5 = 28'd5;
parameter DIVISOR_10 = 28'd10;
always @(posedge clk40)
begin
 if (reset) begin
  clock_out_2 <= 0;
  clock_out_5 <= 0;
  clock_out_10 <= 0;
 end else begin
  counter_2 <= counter_2 + 28'd1;
  counter_5 <= counter_5 + 28'd1;
  counter_10 <= counter_10 + 28'd1;
  if(counter_2>=(DIVISOR_2-1))
   counter_2 <= 28'd0;
  clock_out_2 <= (counter_2<DIVISOR_2/2)?1'b1:1'b0;
  if(counter_5>=(DIVISOR_5-1))
   counter_5 <= 28'd0;
  clock_out_5 <= (counter_5<DIVISOR_5/5)?1'b1:1'b0;
  if(counter_10>=(DIVISOR_10-1))
   counter_10 <= 28'd0;
  clock_out_10 <= (counter_10<DIVISOR_10/2)?1'b1:1'b0;
 end
end
endmodule

---

And here is my corresponding testbench:

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
`timescale 1ns / 1ps
module tb_clock_divider;
 reg clock_in, reset;
 wire clock_out_2, clock_out_5, clock_out_10;
 
 Clock_divider uut (
  .reset(reset),
  .clk40(clock_in),
  .clock_out_2(clock_out_2),
  .clock_out_5(clock_out_5),
  .clock_out_10(clock_out_10)
 );
 
 always
 begin
  clock_in = 1'b0;
 forever
  #400 clock_in = ~clock_in;
 end
 
 initial begin
  reset = 1;
  #800
  reset = 0;
 end
endmodule

---

This code is working fine on behavioral simulation but when I synthesized it and checking the simulation with the synthesized netlist, all the outputs are coming as 0 in the beginning due to reset and then undefined (x) for the rest of the simulation.
I might be missing something here. Can anyone point out the mistake that I am doing here? Thanks in advance!

 

[ThisIsNotSam]

There are some problems with your logic... you are not consistently using reset:

reg[27:0] counter_2=28'd0;
reg[27:0] counter_5=28'd0;
reg[27:0] counter_10=28'd0;

None of these flops is being assigned to zero on gate level because initial assignments are not honored. Your synthesis tool must have warned you about this.

 

[bongosontan]

There are some problems with your logic... you are not consistently using reset:


None of these flops is being assigned to zero on gate level because initial assignments are not honored. Your synthesis tool must have warned you about this.

Hi, yeah that is what I figured out and solved it. Thanks for the reply

 

[bongosontan]

There are some problems with your logic... you are not consistently using reset:


None of these flops is being assigned to zero on gate level because initial assignments are not honored. Your synthesis tool must have warned you about this.

Hi,

I have another question. When I am designing the frequency divider, after place and route the final design is not working as expected. Due to gate delay and interconnect delay, the frequency is changed and it is no longer meeting the divide by 2 or divide by 5 frequency counter. And divide by 10 frequency counter is not working at all. Do you have any idea or info to bypass this errors? It would be very helpful. Thank you!

 

[KlausST]

Hi,

Due to gate delay and interconnect delay, the frequency is changed and it is no longer meeting the divide by 2 or divide by 5 frequency counter. And divide by 10 frequency counter is not working at all.

The "frequency divider" problem is as old as digital electronics.

Thus - since decades (long before FPGAs were invented) - there are many documents, solutions, explanations, even videos ....
Did you at least go through one of them?

If yes:
* post a link to it.
* show your design, your test conditions, your results .. so we can help you to rectify the problem.

Klaus

 

[ThisIsNotSam]

Hi,

I have another question. When I am designing the frequency divider, after place and route the final design is not working as expected. Due to gate delay and interconnect delay, the frequency is changed and it is no longer meeting the divide by 2 or divide by 5 frequency counter. And divide by 10 frequency counter is not working at all. Do you have any idea or info to bypass this errors? It would be very helpful. Thank you!

First check if all the flip-flops you expect to appear on the netlist are actually there. Synthesis will eliminate any flops that it believes are useless, and that will most likely break your design.

Second, gate-level sim is an art form. You gotta make sure you have the right libraries that correspond to your cells, the right verilog `timescale, that delays are properly annotated, and that the simulation is in fact realistic. Several standard cell libraries come with verilog models that have unit delays, i.e., every cell takes 1 time unit to propagate inputs to outputs. This is not enough.