gerade
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lp memory
Hi, all,
did anybody have experience using Dolphin ULP SRAM on tsmc65 GP process?
we have a design that have quite a lot of SRAM(>10Mbit, most of which are dpsram) and we have to sign off the power at FF@125C and 1.1V. And we found the dominating factor is leakage from SRAM. currently we use ARM memory compiler to generate and memory and we would like to know whether there is low power alternative.
If you have any ideal how to reduce the memory power, especially leakage, please kindly share with me!
TNX in advance!
Gerade
Hi, all,
did anybody have experience using Dolphin ULP SRAM on tsmc65 GP process?
we have a design that have quite a lot of SRAM(>10Mbit, most of which are dpsram) and we have to sign off the power at FF@125C and 1.1V. And we found the dominating factor is leakage from SRAM. currently we use ARM memory compiler to generate and memory and we would like to know whether there is low power alternative.
If you have any ideal how to reduce the memory power, especially leakage, please kindly share with me!
TNX in advance!
Gerade