How to use a memory macro in ASIC Flow

[dwindle.fire]

Hello everyone,
I am trying to use a memory macro in my design, but I am not sure how to do that. I have the .lib, .lef, and the .v files created using a memory compiler, and I am using Genus for synthesis. I read in the forum that I have to replace the memory module with an empty module during synthesis so that it can be treated as a black box, but I am not sure how to proceed beyond this. How do I use the .lib and the .v file generated by the memory compiler? Can anyone please mention the steps on how to proceed?
Please help me out. Thanks!

 

[ThisIsNotSam]

the .v is only for simulation, you do not need to provide it to genus
you can synthesize the RTL with the memory instance directly included, it is not an issue. no need for empty/blackbox

 

[dwindle.fire]

the .v is only for simulation, you do not need to provide it to genus
you can synthesize the RTL with the memory instance directly included, it is not an issue. no need for empty/blackbox

Hi, thanks for the quick reply. I tried specifying both the libraries (standard cell library and the .lib generated by memory compiler) in the tcl script, but it seems only the standard cell library is being used. I am not sure whether I am following the proper steps. Would you please elaborate on the steps in a bit more detail? It would help me a lot.

 

[ThisIsNotSam]

there are no steps, really. instead of a single lib, you provide two libs. instead of RTL code without memory, you provide RTL code that has a hard instance of the memory already in it. everything else remains the same.

 

[dwindle.fire]

there are no steps, really. instead of a single lib, you provide two libs. instead of RTL code without memory, you provide RTL code that has a hard instance of the memory already in it. everything else remains the same.

Can you please elaborate on, what you mean by "instead of RTL code without memory, you provide RTL code that has a hard instance of the memory already in it"?
This is the script that I am using for synthesis using Genus. I have specified both the library files, but still, the memory is being replaced by the D-FF from the standard cell library.
set_attribute library {slow.lib sram.lib} read_hdl riscv_soc.v set top_module riscv_core elaborate riscv_core read_sdc constraint_soc.sdc set_attribute leakage_power_effort high synthesize -to_generic synthesize -to_mapped -effort high write_sdf -timescale ns -nonegchecks -recrem split -edges check_edge > syn_report_soc/delays.sdf write_hdl > syn_report_soc/synthesised_netlist.v write_sdc > syn_report_soc/dc_file_for_physical_design.sdc write_script > syn_report_soc/synthesis_script_sdc.g
This is how I have defined the memory block in the RTL. Is this memory block the hard instance? Or do I need to replace this with something else?
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];

Please help me out. Thanks!

 

[ThisIsNotSam]

you need to replace that mem element with a hard instance generated by the memory compiler. your synthesis script is fine, it is your code that is not correct.

 

[dwindle.fire]

I am really sorry, but I don't get what is meant by hard instance here. I have come across this term in some of the other forum posts as well, but it wasn't exactly mentioned what is meant by it. As I had mentioned before I have the .lib, .v files, how should I generate the hard instance out of these files?
I did trying specifying the SRAM instance in the following manner:
SRAM_32x1024_1rw mem(.clk0(clk0), .din0(din0), .dout0(dout0), .addr0(addr0), .csb0(csb0), .web0(web0));
I got the error message that mem is not a register, and I was getting a segmentation fault. After which I commented out all the read-write logic from the verilog code corresponding to the SRAM. Now the code was able to synthesize and I can see in the cell_usage report that the SRAM library is being used. But in the timing report, I can't see any timing arcs from any of the SRAM pins/ports. Now, I am confused about how will the design ensure to which location to read and write from and when? Am I doing it wrong?

[Moderator action: deleted code segment which followed]

 

[ThisIsNotSam]

first: remove the code above from this post, most likely you are not allowed to post it on a public forum
second: it looks like you are mixing behavioral code that still writes into a mem element. such element no longer exists when you instantiate the memory hard instance. your interface to the memory is its ports. nowhere in your code you can have statements like mem[10]<= data. this is not valid. if you don't get it, you need to speak to someone who has done this. ask help from your colleagues, this is a relatively simple everyday task. if you get it right, there will be timing paths that cross the memory instance.