Timing Violation Problem

[tia_design]

Hi, all,

The symptom of my digital part is that:

Chip designed voltage is from 2.5 to 5.5 Volt. The real chip works great at Vdd=3V, but when Vdd=5V, one routine is stucked. If I reduce the external clock from 14MHz to 1MHz, then it works fine. Chip works at room temperature, but same routint is stucked at high temperature, like 100C. Is that because of timing violation. The digital block is a rectangular block, three sides of this block have thick power line, the fourth side is open, will that cause some power drop problem?

Thanks for any comments.

 

[funzero]

Maybe , your design is not simulated in various process voltage temprature. 100C is not recommended for commercail chip. you can modify your PVT parameter , and do STA again.

 

[satyakumar]

Hi,
This type of situtions hapens when you have not taken care about hold time requirements in your design. In CMOS as supply voltage increases the delay reduces, hence if you take a flip flop with increased voltage the contamination delay is reduced so, this violates the hold time requirements.
with temperature the delay increases for typical gate so, there is setup violation with this.

If this is not correct, feel free to comment.

Thanks and regards
satyakumar

 

[avimit]

The thing is : your chip is not showing consistant resutls:
Lowering the frequency makes it work: means its a setup problem
Raising the voltage then should also make it work, but its failing, which suggests a hold porb:
Raising the temperature makes it fail: Again setup prob suspected.

So,
1. Make sure that you are varing only one parameter at one time.
2. Try to get consistant results: Same path is not likely fail for both setup and hold. So even if the same routine is failing, there may be 2 paths involving the same routine, one fails due to setup and the other due to hold.

My recommendation:
Do a full chip STA at different corners. You will surely see what path is failing. I dont think Power rail should have anything to do with it
Hope it helps.
Kr,
Avi
http://www.vlsiip.com