Register recovery/removal violation

[kaz1]

This is about timing violations at async reset release. Implementing it and synchronising it is dead easy. but my question is about underlying concepts.

In FPGA vendor or user literatures I find it hard to fully understand the concept of recovery/removal. So Thought may be ASIC designers can shed some light.

Async reset release timing violation relates to sampling window defined as:
Recovery is equivalent to "setup violation at reset release" and Removal is equivalent to "hold violation at reset release".

So it relates to sampling window which originally is meant for D input yet there is no clear discussion on relevance of D input and whether it contributes to the concept or not.
I also read that if the register is going to change internal state due to change (at D input or Q output) then reset release becomes critical otherwise it does not matter.

If so how to reconcile (D , internal state, Q output) as relevant., or is it only D state coinciding with reset release that causes concern?

Thanks

 

[ThisIsNotSam]

Think about setup and hold as an input data stability problem, don't think about D pins.

In a flip-flop, when the clock comes, input must have remained stable for setup_X time units and must remain stable for hold_Y time units. Now instead of input data you have reset. Input must remain stable for some time before and after a clock edge. That is all there is to it, simple concept.

 

[kaz1]

Thanks that is very simple but I hope it is not simpler...
Your reply raises another question: is setup and hold figures (usually of D input relative to clock edge) apply equally and exactly to async input which is unrelated to clock edge?

--- Updated Oct 4, 2023 ---

Firstly in my first post I made naming error, it should say:
Removal is equivalent to "setup violation at reset release" and Recovery is equivalent to "hold violation at reset release".

After some research I found this Intel statement somehow improving on the concept of relation to D input capture:

"The reset Removal Check ensures that the de-asserted reset signal is not captured by the same clock edge that launches the reset."

Here is the link to the document:

1.2.1.1. Recovery and Removal Checks

www.intel.com