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SPI timing constraints


Member level 2
May 21, 2021
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Does anyone know SPI timing constraints that comes from vendor - does that support all CPOL CPHA based 4 modes?

We heard back from vendor it does, but i am not sure how that works out. We plan to run ext clock at 62.5 mhz, ext refclk is 250 mhz, apb / pclk is 125 mhz.

Any help is much appreciated!

most probably you want to connect some SPI devices to the bus. Each of these devices comes with a datasheet. In these datasheets the timing is specified.
If you design your SPI to match your connected devices you are safe.

If i have IO pads related to SPI protocol..are we saying i should enquire about the other side of the IO pads and accordingly proceed with timing constraints?

Disclaimer - havent done this before - so i really dont know how to go about this. We do have vendor constraints but i really want to be sure i'm not missing something.

Am I right that you desing an SPI_Master?

Motorla - I think - first used/developed SPI. As far as I know there is no continously updated SPI specification.
In opposite to I2C SPI has no specified frequencies, nor frequency limits. Thus my above recommendation to refer to the used SPI_slaves datasheets.

I designed SPI (master as well as slave) into PLDs. I did it just the straight forward (and also simple) way:
* 50% duty cycle SPI_clock
* outputting data at one SPI_clock_edge
* inputting data on the opposite clock edge

As SPI_Master I used DFFs at each SPI output (SS, SCK, MOSI) .. to get most perfect aligned edges.
And as SPI_slave I used SPI_clock to latch_in (DFF) MOSI .. as well as latch_out (DFF) MISO data.


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