Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][2]

[abu9022]

Timing violation in VCS simulation

Hi friends,

can you help me how to solve the below problem

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][3]
    $setuphold( posedge CK:110, posedge D:110, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][4]
    $setuphold( posedge CK:110, posedge D:110, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][2]
    $setuphold( posedge CK:110, posedge D:110, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][5]
    $setuphold( posedge CK:110, posedge D:110, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][1]
    $setuphold( posedge CK:110, posedge D:110, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][0]
    $setuphold( posedge CK:110, posedge D:110, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][3]
    $setuphold( posedge CK:190, posedge D:190, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][4]
    $setuphold( posedge CK:190, posedge D:190, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][2]
    $setuphold( posedge CK:190, posedge D:190, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][5]
    $setuphold( posedge CK:190, posedge D:190, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][1]
    $setuphold( posedge CK:190, posedge D:190, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][0]
    $setuphold( posedge CK:190, posedge D:190, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][3]
    $setuphold( posedge CK:270, posedge D:270, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][4]
    $setuphold( posedge CK:270, posedge D:270, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][2]
    $setuphold( posedge CK:270, posedge D:270, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][5]
    $setuphold( posedge CK:270, posedge D:270, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][1]
    $setuphold( posedge CK:270, posedge D:270, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][0]
    $setuphold( posedge CK:270, posedge D:270, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][3]
    $setuphold( posedge CK:350, posedge D:350, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][4]
    $setuphold( posedge CK:350, posedge D:350, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][2]
    $setuphold( posedge CK:350, posedge D:350, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][5]
    $setuphold( posedge CK:350, posedge D:350, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][1]
    $setuphold( posedge CK:350, posedge D:350, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][0]
    $setuphold( posedge CK:350, posedge D:350, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][3]
    $setuphold( posedge CK:430, posedge D:430, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][4]
    $setuphold( posedge CK:430, posedge D:430, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][2]
    $setuphold( posedge CK:430, posedge D:430, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][5]
    $setuphold( posedge CK:430, posedge D:430, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][1]
    $setuphold( posedge CK:430, posedge D:430, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][0]
    $setuphold( posedge CK:430, posedge D:430, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][3]
    $setuphold( posedge CK:510, posedge D:510, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][4]
    $setuphold( posedge CK:510, posedge D:510, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][2]
    $setuphold( posedge CK:510, posedge D:510, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][5]
    $setuphold( posedge CK:510, posedge D:510, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][1]
    $setuphold( posedge CK:510, posedge D:510, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][0]
    $setuphold( posedge CK:510, posedge D:510, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][3]
    $setuphold( posedge CK:590, posedge D:590, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][4]
    $setuphold( posedge CK:590, posedge D:590, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][2]
    $setuphold( posedge CK:590, posedge D:590, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][5]
    $setuphold( posedge CK:590, posedge D:590, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][1]
    $setuphold( posedge CK:590, posedge D:590, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][0]
    $setuphold( posedge CK:590, posedge D:590, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][2]
    $setuphold( posedge CK:594, posedge D:594, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][1]
    $setuphold( posedge CK:594, posedge D:594, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][4]
    $setuphold( posedge CK:594, posedge D:594, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][5]
    $setuphold( posedge CK:594, posedge D:594, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][0]
    $setuphold( posedge CK:594, posedge D:594, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][3]
    $setuphold( posedge CK:594, posedge D:594, limits: (0,1) );

 

[ads-ee]

It looks like the clock (CK) and the data (D) are switching at exactly the same time. I suspect that you have a design issue as that would be something you would normally avoid doing.

It looks like you are trying to run a gate level simulation without an SDF? If so you should probably add +notimingchecks to your simulation command line.

 

[abu9022]

It looks like the clock (CK) and the data (D) are switching at exactly the same time. I suspect that you have a design issue as that would be something you would normally avoid doing.

It looks like you are trying to run a gate level simulation without an SDF? If so you should probably add +notimingchecks to your simulation command line.

Hi ads-ee,

I need to run Logic Simulation(Gate Level Simulation) with the SDF file, so what i need to do?

How to solves the design issues?
what kind of design issue

 

[abu9022]

I asked my professor about this error, he told there is a Hold Time violation, can anybody help me How to solve this

I am using below script to generate SDF file, can you check script is correct or I need to include something?

# list of all HDL files in the design
set myFiles [list leon/std_logic_signed.vhd leon/std_logic_unsigned.vhd leon/std_logic_arith.vhd leon/amba.vhd leon/target.vhd leon/device.vhd leon/config.vhd leon/sparcv8.vhd leon/mmuconfig.vhd leon/iface.vhd leon/macro.vhd leon/bprom.vhd leon/multlib.vhd leon/tech_generic.vhd leon/tech_virtex.vhd leon/tech_virtex2.vhd leon/tech_atc18.vhd leon/tech_atc25.vhd leon/tech_atc35.vhd leon/tech_fs90.vhd leon/tech_tsmc25.vhd leon/tech_umc18.vhd leon/tech_proasic.vhd leon/tech_axcel.vhd leon/tech_map.vhd leon/mmu_icache.vhd leon/mmu_dcache.vhd leon/mmu_acache.vhd leon/mmutlbcam.vhd leon/mmulrue.vhd leon/mmulru.vhd leon/mmutlb.vhd leon/mmutw.vhd leon/mmu.vhd leon/mmu_cache.vhd leon/cachemem.vhd leon/icache.vhd leon/dcache.vhd leon/acache.vhd leon/cache.vhd leon/ambacomp.vhd leon/apbmst.vhd leon/ahbmst.vhd leon/ahbstat.vhd leon/ahbtest.vhd leon/ahbram.vhd leon/ahbarb.vhd leon/lconf.vhd leon/fpulib.vhd leon/fpu_lth.vhd leon/meiko.vhd leon/fpu_core.vhd leon/grfpc.vhd leon/fp1eu.vhd leon/ioport.vhd leon/irqctrl.vhd leon/irqctrl2.vhd leon/sdmctrl.vhd leon/mctrl.vhd leon/rstgen.vhd leon/timers.vhd leon/uart.vhd leon/mul.vhd leon/div.vhd leon/iu.vhd leon/dcom_uart.vhd leon/dcom.vhd leon/dsu_mem.vhd leon/dsu.vhd leon/proc.vhd leon/wprot.vhd leon/mcore.vhd leon/leon.vhd]


#set basename leon
set my_toplevel iu
set fileFormat vhdl
set my_clock_pin clk

set my_period 7.0
#set my_clk_freq_MHz 166.7
#set clock_skew = 0.10
set my_input_delay_ns 0.0
set my_output_delay_ns 0.0
set my_flatten 1;  ##one yes, zero no

#set myClk clk
#set myPeriod 4;
#set myClkLatency_ns 0.0
#set myInDelay_ns 0.0
#set myOutDelay_ns 0.0

set search_path "$search_path /home/ee5323/mwj894/Nangate"
set target_library  "NangateOpenCellLibrary_slow_conditional_nldm.db";
set link_library  "* NangateOpenCellLibrary_slow_conditional_nldm.db";




#set search_path "$search_path /home/bliu/Desktop/owahid_download/leon/leon2-1.0.30-xst/Nangate"
#set target_library  "NangateOpenCellLibrary_slow_conditional_nldm.db";
#set target_library  "NangateOpenCellLibrary_slow_conditional_nldm.db";
#set link_library  "* NangateOpenCellLibrary_slow_conditional_nldm.db";


#set search_path "$search_path /home/bliu/Desktop/owahid_download/leon/leon2-1.0.30-xst/FreePDK45/osu_soc/lib/files"
#set target_library  "gscl45nm.db";
#set link_library  "* gscl45nm.db";



#hdlin_ff_always_sync_set_reset = true
#hdlin_translate_off_skip_text = true

set alib_library_analysis_path $search_path
define_design_lib WORK -path ./work
set verilogout_show_unconnected_pins "true"
#set vhdlout_unconnected_pin_prefix
#set_ultra_optimization true
#set_ultra_optimization -force

analyze -format $fileFormat -lib WORK $myFiles
elaborate $my_toplevel
current_design $my_toplevel
link
uniquify

#set my_period [expr 1000 / $my_clk_freq_MHz]

set find_clock [ find port [list $my_clock_pin] ]
if {  $find_clock != [list] } {
   set clk_name $my_clock_pin
   create_clock -period $my_period $clk_name
} else {
   set clk_name vclk
   create_clock -period $my_period -name $clk_name
}

set_input_delay $my_input_delay_ns -clock $clk_name [remove_from_collection [all_inputs] $my_clock_pin]
set_output_delay $my_output_delay_ns -clock $clk_name [all_outputs]

if { $my_flatten == 1} {
    compile -ungroup_all -map_effort medium
} elseif { $my_flatten == 0} {
    compile -map_effort medium
}
compile_ultra
check_design
check_timing
report_constraint -all_violators

#write -f db -hier -output leon_synth_166.7mhz_db.db
write -f verilog -output iu_verilog7ns.v
write -f vhdl -output iu_vhdl7ns.vhd
write_sdc iu_verilog7ns.sdc
write_sdf iu_verilog7ns.sdf

report_area > iu_verilog7ns.area
report_timing > iu_verilog7ns.timing
report_power > iu_verilog7ns.power

report_timing -nets -path full -delay max -nworst 5000 -max_paths 5000 > iu_verilog7ns.5000worst
report_timing -nets -path full -delay max -greater_path 2.0 -max_paths 5000 > iu_verilog7ns.5000greater2ns

 

[sharath666]

This is a synthesis script. It does not make any sense running gate simulation with a post synthesis netlist with a SDF. You should not use an SDF in this setup. SDF is only used with a post layout netlist.

 

[abu9022]

This is a synthesis script. It does not make any sense running gate simulation with a post synthesis netlist with a SDF. You should not use an SDF in this setup. SDF is only used with a post layout netlist.

Above Script for Converting vhdl to verilog for gate level simulation

Below script for verilog to verilog_standard Input and Ouput. SDF file are used from this script

# list of all HDL files in the design
remove_design -design
set myFiles [list iu_verilog7ns.v]

#set basename leon
set my_toplevel iu
set fileFormat verilog
set my_clock_pin clk

set my_period 7.0
#set my_clk_freq_MHz 166.7
#set clock_skew = 0.10
set my_input_delay_ns 0.0
set my_output_delay_ns 0.0
set my_flatten 1;  ##one yes, zero no

#set myClk clk
#set myPeriod 4;
#set myClkLatency_ns 0.0
#set myInDelay_ns 0.0
#set myOutDelay_ns 0.0

set search_path "$search_path /home/ee5323/mwj894/Nangate"
set target_library  "NangateOpenCellLibrary_slow_conditional_nldm.db";
set link_library  "* NangateOpenCellLibrary_slow_conditional_nldm.db";


#hdlin_ff_always_sync_set_reset = true
#hdlin_translate_off_skip_text = true

set alib_library_analysis_path $search_path
define_design_lib WORK -path ./work
set verilogout_show_unconnected_pins "true"
#set ungroup_keep_original_design "true"
#set vhdlout_unconnected_pin_prefix
#set_ultra_optimization true
#set_ultra_optimization -force
#read_verilog iu_milad_final.v
read_file -netlist -format $fileFormat $myFiles
elaborate $my_toplevel
current_design $my_toplevel
link
uniquify
set find_clock [ find port [list $my_clock_pin] ]
if {  $find_clock != [list] } {
   set clk_name $my_clock_pin
   create_clock -period $my_period $clk_name
} else {
   set clk_name vclk
   create_clock -period $my_period -name $clk_name
}

set_input_delay $my_input_delay_ns -clock $clk_name [remove_from_collection [all_inputs] $my_clock_pin]
set_output_delay $my_output_delay_ns -clock $clk_name [all_outputs]
#if { $my_flatten == 1} {
 #  compile -ungroup_all -map_effort medium
#} elseif { $my_flatten == 0} {
#    compile -map_effort medium
#}
#compile_ultra
check_design
check_timing
report_constraint -all_violators

#write -f db -hier -output leon_synth_166.7mhz_db.db
write -f verilog -output iu_verilog7nsStdInOut.v
write -f vhdl -output iu_vhdl7nsStdInOut.vhd
write_sdc iu_verilog7nsStdInOut.sdc
write_sdf iu_verilog7nsStdInOut.sdf

report_area > iu_verilog7nsStdInOut.area
report_timing > iu_verilog7nsStdInOut.timing
report_power > iu_verilog7nsStdInOut.power

report_timing -nets -path full -delay max -nworst 5000 -max_paths 5000 > iu_verilog7nsStdInOut.5000worst
report_timing -nets -path full -delay max -greater_path 2.0 -max_paths 5000 > iu_verilog7nsStdInOut.5000greater2ns

 

[sharath666]

1. I don't know why you are converting a VHDL setup to a verilog setup.(Ok..looks like your libraries are in verlog)
2. The SDF files generated by both setups should be the same.
3. My argument of not using the SDF in the first place still holds true...To explain it further, a post synthesis netlist does not have any routing delays since routing has not taken place. So ideally you should be running a unit delay simulation on this netlist or you should wait till you get a post layout netlist and then use the SDF generated by primetime to run GLS.

 

[FvM]

I think there are different ways to get timing violations in gate level simulation:
- the design itself involves design flaws that can't be fixed by the synthesis tool
- a basically correct design is synthesized with inappropriate timing constraints
- a faulty testbench
- wrong gate level library used

But how can we know without any design details?

- - - Updated - - -

I now got sharath666's point. Another option, running the wrong analysis.