Timing Simulation with Altera-Modelsim

[faust861]

Hello to all,
I'm new at working on CPLD in VHDL. Fortunately, I knew this language from University and I can understand and write it quite well.
Maybe, the greatest difficulties are the settings of the softwares.
I use Quartus II 9.1 SP2 and Altera-Modelsim 6.5b.

I made a project about a PWM. I also made a testbench for the Functional Simulation and it works quite well. Now, I would like to learn to do the Timing Simulation, but I can't understand how to do it.

I know that I need two files: the netlist (.vho) and the .sdo file.
In some way, I could obtain these files (in EDA Tool Settings, under Timing Analysis, I choose "Custom" with Format to Output Netlist "VHDL").

Now I have to use them in Modelsim. I could understand that:
1) In the library work of the project, I have to compile the vho file;
2) In the Simulation menu, I choose "Start simulation", on the tab "SDF" I open my .sdo file
3) In the "Start simulation" window again, on the tab design, I choose my top entity (not the testbench)

The simulation is ready to start, but there isn't any clock or stimulus to simulate...this is easy to understand, because in the functional simulation, that information were in the testbench...
But if I choose the testbench instead of the top entity in point 3), the vsim tells me errors about "No default binding for components"...

My questions:
A) am I doing anything wrong or this way is right?
B) have I got to set my stimuli in the .vho file? and in this case how?
C) what about .sdf max, min, latest? I understand that they are like constraints, so my simulation can tell me if they are not met, is it right? and how to set them?
D) it is important to set "Apply to Region" field in my point 2)? what is to be set there? the top level entity? in which format?
E) philosophically, is it important to do timing simulation if timing requirements are already met in classic time analyzer on Quartus II? (I set a Fmax of 100 Mhz)
F) this is a little off topic: why if I use Time Quest instead of Classic Time Analyzer, the requirement about the Fmax isn't met? (it tells me a Fmax of about 94 Mhz)

Thank you for the patience and the disponibility

ps: the device I use is from Max II family, if this can be useful.

 

[ljxpjpjljx]

questasim or modelsim?

 

[faust861]

ModelSim Altera Starter Edition 6.5b

 

[devas]

Hi,

Maybe easier is to select Simulation instead of Timing Analysis in the Quartus settings. In this tab you can enable Run gate-level simulation. I have never used it, but it could help you. Specifying a tool name here will also generate a vho (VHDL netlist) and sdo file.

Otherwise, compile the vho file to the library. Maybe modify your testbench so it instantiates the vho toplevel unit correctly (name, port names).
Start the simululation on your testbench and select in the SDF tab the generated sdo file.
Than, important, set the correct "Apply to region". When you do not fill in this field, it will start on your toplevel, what is your testbench. As the sdo file has been generated for your vho file, you get error messages. You must apply the instantiation name of your vho toplevel in your testbench.
For example, your testbench contains:
uut: my_design port map(......);
You must apply "/uut" as region.

Succes, Devas

 

[faust861]

Devas, thank you for the reply. It was very useful.

I think I'm very very close, but I have still problems.
The first thing I would say is that compiling the vho generate a new architecture for my top-level entity. So if I click on + of this entity, it shows me 2 architectures: mine and one named "structure", derived from the compiling of the vho.

The differency between the 2 architectures about the declaration of entity is the generic field: vho ignores generic.
But when I try to run my testbench, it gives me errors about the default binding for component like:
"Generic 'dim' is not on the entity."

It seems that only these gives problems

edit: ok, it works if I run it from the Library window and not from the Start simulation/ Tab "Design"

the simulation is strongly slower, but I think it's due to timing simulation, so it's a good sign
Now I have to understand why the circuit doesn't work! Maybe the clock (100 MHz) is too fast, even if the Classic Time Analyzer in Quartus II said me it was good?

 

[devas]

Hi,

Be sure that the new architecture 'structure' is used (compiling the vho file as latest, it should be, but it is always good to verify). Modelsim Transcript window shows the entity/architectures it loads for the simulation. It should show something like:
# Loading work.my_design(structure)

Second be sure that it loads the SDF file. I am not sure it will when you start the simulation from the library window. It should show this in the Modelsim Transcript window behind Modelsim>:
ModelSim> vsim work.my_testbench "something with SDF and your SDF file"

That your simulation is slow is a good sign, but that it is not behaving as expected not :wink:

When it is not working I suppose the transcript window shows setup and hold violations (you can get these violations even when your design is simulating correctly).

Success, Devas