Timing question with combinational gates

[Qwerty112233]

When we have let's say, NAND gate on clock path..does that change timing edges and checks for setup and hold?

Seeing a rise edge flop that is getting timed at falling edge for hold..but it shows NAND cell in the path so i'm curious how these non buffer/inverter clock logic cells change timing?

 

[ThisIsNotSam]

In general, this is not the behavior that the tools implement in the clock tree. They typically keep the same clock polarity. It might be possible that what you are describing is enabled by some advanced setting, but I cannot be sure.

 

[KlausST]

Hi,

please draw a sketch so we can see the path of clock and also data.

Klaus

 

[Qwerty112233]

Ah, I looked at the path closer and found that clock path started with falling edge because there's a XNOR gate inverting polarity in the clock arc. Trying to understand what needs to be done wrt clock path cells.

 

[KlausST]

Hi,

This is what you should avoid.

You should feed the global clock to the DFF and do the rest with the DFF_enable.
This is why there is a global clock.

Klaus