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Solution to interview question about coding

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anantha_09

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can any one clearly explain?

In verilog what is the difference between

c = foo ? a : b;

and

if (foo) c = a; else c = b;
 

Old Nick

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Re: interview question

c=foo ? a:b;

it may be easier to visualise this code in use

assign out = (c=foo) ? a:b;

if c=foo then the result of the expression is a (out = a)
if not then the output of the expression is b (out = b)
c is not set to anything

if (foo) c = a; else c = b;

if foo is true (=1) then
c=a
if foo=0
c=b

I hope that helps!
 

sanjay11

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Re: interview question

Just check with any simulator
what is the output value if foo == 1'bx

Regards,
Sanjay
 

alam.tauqueer

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interview question

First one will be a mux with select is "c".Second one will be implemented using priority encoder.
 

salma ali bakr

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Re: interview question

c = foo ? a : b;

if "c" equals "foo" then the output is "a"
otherwise the output is "b"
but you have to give this expression to some signal "output"


if (foo) c = a; else c = b;

this is a normal if statement
if foo=1 (foo is true) then c=a
if foo=0 (foo is false) then c=b
 

lakshman.ar

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interview question

with the synthesis perspective, the first statement synthesizes to "MUX" and the second one synthesizes to a "PRIORITY ENCODER"
 

lordsathish

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Re: interview question

Hey i think both are synthesised as muxes only...
i also verified with the synthesis tool...i think actually there is no difference between the two statements in synthesis perspective...
 

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interview question

Hi,
Like mentioned by Old Nick and Salma the difference is the test condition and these two expressona are very different so synthesis gives differents results.

Cheers,
Master_picengineer
 

lordsathish

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Re: interview question

hey but i got different results...
for the followinf code my synthesis results was muxes

module muxorenc(a,b,c,d,foo) ;
input a,b,foo;
output c,d;
reg d;
assign c= foo ? a:b;

always @(a or b or foo)
begin
if(foo)
d=a;
else
d=b;
end
endmodule
this is the synthesis output i got...

[/img]
 

santhosh.mandugula

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Re: interview question

If case infers- D-ff and the ternary operator statement infers mux with 'foo' as control signal
 

vamsi_addagada

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interview question

hi anantha

The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10, and b = 'b11, you'd get c = 'b1x. On the other hand, if treats Xs or Zs as FALSE, so you'd always get c = b.

vamsi
 

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interview question

Don't be surprised lordfush that normal and was expected!
 

salma ali bakr

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Re: interview question

the ternary operator synthesizes to a mux and it's regarded as combinational modeling with the statement assign...
while the if statement synthesizes to priority encoded logic

for making sure the if statements written are synthesized well...put in mind that:

*all outputs should be defined in all branches of the statement, cause if not it will create latches...you can avoid the latches headache by writing default values for all outputs before the if statement..

**you should limit the number of input signals into an if statement, in order to reduce the number of logic levels...
 

avimit

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Re: interview question

There is absolutely no difference between the two. Synth, sim will give same results. No priority encoder. priority encoder is inferred when you use 'else if' not just else.
Kr,
Avi
https://www.vlsiip.com
 

salma ali bakr

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Re: interview question

well...for me...i was talking about the nested if else in general...but for a simple if else...it would be just a mux of course
 

lordsathish

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Re: interview question

avimit said:
There is absolutely no difference between the two. Synth, sim will give same results. No priority encoder. priority encoder is inferred when you use 'else if' not just else.
Kr,
Avi
https://www.vlsiip.com

Thanks avimit... since the day i started learing HDL i've been told that such an if else would synthesis as a mux... i got bit confused by few replies... i think they wouldn have carefully noticed the statement....
 

bharat_in

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Re: interview question

@lordsathish
As per your earlier comment it is clear that, after synthesis there is no difference between this two, But in simulation when foo = 1'bx, ternary operator (?) is mergeing a and b, while if/else is selecting signal b as output.

Now, this is something which can lead to pre-synthesis and post-synthesis simulation mismatch.

I don't have any such tool for post-synthesis simulation, can anyone please give it a shot and share the result?
 

shiv_emf

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Re: interview question

nice discussion here....

yeah there will be mismatches ! for post n pre synthesis simulation mismatches !

Added after 1 minutes:

lordsathish said:
hey but i got different results...
for the followinf code my synthesis results was muxes

module muxorenc(a,b,c,d,foo) ;
input a,b,foo;
output c,d;
reg d;
assign c= foo ? a:b;

always @(a or b or foo)
begin
if(foo)
d=a;
else
d=b;
end
endmodule
this is the synthesis output i got...

[/img]

foo in sensitivity list ? is it required?
it may form combination loop ...

oh i ws wrong i thot foo is output thr
 

santoshl

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Re: interview question

Hi,
as per my knowledge........c==foo?a:b will be implemented as a ordinary mux while the other form is implemented as priority encoder. As there are only two states ( absence of elseif ) priority encoder is same as mux. Hence we will c no difference in simulator.

Hope it clarify things

Santosh L
 

bharat_in

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Re: interview question

@santhoshi...
Well, you can implement priority encoder with ternary operator also...
like,
Code:
 c==foo? a : ( foo2 ? b : c);
This will be same as if/elseif/else, and will create priority encoder.

In simulation it will have problem only when selection line is "X". Otherwise there is no difference after synthesis, whether you implement with ternary or if/else?
 

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