Guard ring question

[Qwerty112233]

If you need to isolate certain standard cells separate from other cells in the design, we will need to cut standard cell rows around these cells? Then draw a ring in OD (oxide diffusion), NW, PW layers?

will that suffice? These layers OD, PW and NW need to be tied off to power nets..Will this work?

 

[dick_freebird]

I'd recommend that different supply domains be kept separate and
each one "its own thing", and work outward from the done block.
I wouldn't want to route multiple supplies in a standard cell sea.
Too easy to "oops" something, get simulations that work and
verification that passes, until you put real power to real part.

Look to the I/O & ESD guardring stuff in the design docs, don't
be afraid to go over the top on nested rings if you feel like some
block is especially prone to substrate current injection (like using
substrate PNPs, or driving an inductive external load...).

 

[ThisIsNotSam]

If you need to isolate certain standard cells separate from other cells in the design, we will need to cut standard cell rows around these cells? Then draw a ring in OD (oxide diffusion), NW, PW layers?

will that suffice? These layers OD, PW and NW need to be tied off to power nets..Will this work?

std cell libraries come with power-specific cells that do this for you. you should not be drawing any OD or well in a digital design. check your libraries' documentation.