Regarding I/O pins for ASIC design

[swathipushpa]

Hai,

I am working on a verilog code for ASIC design wherin i have a limitation on the number of I/O pins being provided. My design consists 128 bit input and 128 bit output along with some control signals being provided paralelly..

So now my question is, how can i make my design to reduce the number of pins accordingly, so as to design an ASIC with 32 pins.???

Thank you :smile::???:

 

[birdy123]

Hi ,

I will suggest you to do in in other way.. means increase the no of input signal..

One way is .. you decoder or mux. In this you have to see in your design which particular part of the design is independent to each other and then accordingly you can control those through any control signal.

You can say that the obove mention way is another way of reducing the no of pins of your design.

Let me know if it helpful to you or not. If you need any specific detail let meknow.