looks like i misunderstood the question. if you want a delay the clock by a certain period of time, then the answer for that is shift register and this is the code.
module sht_reg(raw_clk,rst,ddr_clk);
input raw_clk;
input rst;
output ddr_clk;
reg ddr_clk;
reg [7] shift_reg;
always@(posedge raw_clk or negedge rst)
begin
if(!rst)
begin
shift_reg <= 8'b0;
ddr_clk <= 1'b0;
end
else
begin
ddr_clk <= shift_reg[0];
shift_reg <= {raw_clk,shift_reg[7]};
end
end
endmodule
ofcourse, instead of 7:0, u can declare a parameter called delay and have [delay] and have the delay configurable one during simulation.
Added after 21 minutes:
to be frank, ur initial idea is also the same, only, i have realized as a bunch of registers and u have done it as individual registers.