EDA_hg81
Advanced Member level 2

delay registers in verilog
Getting data setup errors from source to destination.
I am trying use code as following to realize clock delay.
reg Clock;
reg REG1;
reg REG2;
reg REG3;
reg REG4;
reg REG5;
reg REG6;
reg REG7;
reg REG8;
wire DDR_Clock;
assign DDR_Clock = Clock;
always @ (RAWClock)
begin
REG1 <= RAWClock;
REG2 <= REG1;
REG3 <= REG2;
REG4 <= REG3;
REG5 <= REG4;
REG6 <= REG5;
REG7 <= REG6;
Clock <= REG7;
end
always @ (posedge DDR_Clock)
begin
more code;
end
Do you think I can realize this idea?
Thank you.
Getting data setup errors from source to destination.
I am trying use code as following to realize clock delay.
reg Clock;
reg REG1;
reg REG2;
reg REG3;
reg REG4;
reg REG5;
reg REG6;
reg REG7;
reg REG8;
wire DDR_Clock;
assign DDR_Clock = Clock;
always @ (RAWClock)
begin
REG1 <= RAWClock;
REG2 <= REG1;
REG3 <= REG2;
REG4 <= REG3;
REG5 <= REG4;
REG6 <= REG5;
REG7 <= REG6;
Clock <= REG7;
end
always @ (posedge DDR_Clock)
begin
more code;
end
Do you think I can realize this idea?
Thank you.