How can I run verilog code with data at a specific time in the past?

[alexis57]

Hello,
My simulation takes hours until it's stopped from my SystemVerilog code using $stop;$s⊤;

When it stops, to have proper information, I need to run a verilog task/function at a certain time before it stopped. The function reads the memory and prints various information.
Is there a way to do that?

Otherwise, what would be the appropriate alternative?

How do verification engineers debug such a situation?

There is the "call" tcl command but it doesn't have the time parameter and once the error happened, it's too late. "examine" maybe?

Regards,

 

[BradtheRad]

I need to run a verilog task/function at a certain time before it stopped.

There are two methods we might decide to read time in a simulation: a) computer's real-time clock, or b) simulation time. If we could figure out which answers our need we'd know how to go ahead. Even if we write code to mimic a clock, it's a puzzle how many seconds of real-time equals a second of simulation time. Each are in our realm.

Instead I think putting a simple counter inside your code is the way to go. Increment the count each time it enters a routine, or each time it reads data, or stores data. (Display verbose reports onscreen if that will help). Periodically compare the count to some desired value. When they match, display the final information. You might need to do trial runs to get things done before the simulation halts.

 

[ThisIsNotSam]

Hello,
My simulation takes hours until it's stopped from my SystemVerilog code using $stop;$s⊤;

When it stops, to have proper information, I need to run a verilog task/function at a certain time before it stopped. The function reads the memory and prints various information.
Is there a way to do that?

Otherwise, what would be the appropriate alternative?

How do verification engineers debug such a situation?

There is the "call" tcl command but it doesn't have the time parameter and once the error happened, it's too late. "examine" maybe?

Regards,

You don't have to do this in verilog per se. Look into your simulator capabilities for probing.