alexis57
Newbie
Hello,
My simulation takes hours until it's stopped from my SystemVerilog code using $stop;$s⊤;
When it stops, to have proper information, I need to run a verilog task/function at a certain time before it stopped. The function reads the memory and prints various information.
Is there a way to do that?
Otherwise, what would be the appropriate alternative?
How do verification engineers debug such a situation?
There is the "call" tcl command but it doesn't have the time parameter and once the error happened, it's too late. "examine" maybe?
Regards,
My simulation takes hours until it's stopped from my SystemVerilog code using $stop;$s⊤;
When it stops, to have proper information, I need to run a verilog task/function at a certain time before it stopped. The function reads the memory and prints various information.
Is there a way to do that?
Otherwise, what would be the appropriate alternative?
How do verification engineers debug such a situation?
There is the "call" tcl command but it doesn't have the time parameter and once the error happened, it's too late. "examine" maybe?
Regards,
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