Making delay using Verilog code

[EDA_hg81]

delay registers in verilog

Getting data setup errors from source to destination.

I am trying use code as following to realize clock delay.

reg Clock;
reg REG1;
reg REG2;
reg REG3;
reg REG4;
reg REG5;
reg REG6;
reg REG7;
reg REG8;
wire DDR_Clock;

assign DDR_Clock = Clock;
always @ (RAWClock)
begin
REG1 <= RAWClock;
REG2 <= REG1;
REG3 <= REG2;
REG4 <= REG3;
REG5 <= REG4;
REG6 <= REG5;
REG7 <= REG6;
Clock <= REG7;
end

always @ (posedge DDR_Clock)
begin
more code;
end

Do you think I can realize this idea?

Thank you.

 

[sree205]

why don't u just use a 3 bit counter ? it ll infer lesser hardware and still give u the same delay as the idea u have described.

 

[EDA_hg81]

Would you like write a sample code for me .

Thank you.

 

[sree205]

module cnt(rst,raw_clk,ddr_clk);

input raw_clk,rst;
output ddr_clk;
reg ddr_clk;
reg [2] cnt;

always@(posedge raw_clk or negedge rst)
begin
if(!rst)
begin
cnt <= 3'b0;
ddr_clk <= 1'b0;
end
else
begin
cnt <= cnt+1'b1;
if(cnt==3'b111)
ddr_clk <= 1'b1;
else
ddr_clk <= 1'b0;
end
end
endmodule

Added after 1 minutes:

ofcourse, you won't get a 50% dutycycle clock. i'm assuming you are going to use the posedge of clock. this should satisfy ur criteria.

 

[EDA_hg81]

Very appreciate for your help!


Added after 58 minutes:

one more quextion.

How can I constrian the new clock, use constrian editor?

Thank you.

 

[kib]

what is ur requirement?
to delay the clock or to divide the clock?
what code sree205 has written is a clock divider

 

[EDA_hg81]

I just want to delay the clock for a while.


Do you have any idea?

 

[sree205]

looks like i misunderstood the question. if you want a delay the clock by a certain period of time, then the answer for that is shift register and this is the code.


module sht_reg(raw_clk,rst,ddr_clk);

input raw_clk;
input rst;
output ddr_clk;
reg ddr_clk;
reg [7] shift_reg;

always@(posedge raw_clk or negedge rst)
begin
if(!rst)
begin
shift_reg <= 8'b0;
ddr_clk <= 1'b0;
end
else
begin
ddr_clk <= shift_reg[0];
shift_reg <= {raw_clk,shift_reg[7]};
end
end

endmodule


ofcourse, instead of 7:0, u can declare a parameter called delay and have [delay] and have the delay configurable one during simulation.

Added after 21 minutes:

to be frank, ur initial idea is also the same, only, i have realized as a bunch of registers and u have done it as individual registers.

 

[EDA_hg81]

sree205

Thank you for your help.

 

[sree205]

no probs man. here is a checklist document on successful synthesis with constraints.

 

[kib]

i would recommend you to use a dcm for delaying the clock.
above code (shift register approach) may have serious timing problem on an FPGA

 

[sree205]

what u r suggesting is to phase shift the clock, if i'm not mistaken. maybe EDA_hg81 can tell how much of delay he wants exactly.

 

[EDA_hg81]

I am using spartan 2e, but his guy does not have DCM.

I have to find my way to delay this clock.

your suggestions all are great.

Thank you all and have a good weekend.

 

[sree205]

yes, u r right. these r the devices for which DCM is supported.

Virtex-II, Virtex-II Pro, Virtex-II Pro X, Virtex-4, Spartan-3, Spartan-3L devices

Added after 37 seconds:

let me know ur clock frequency and the delay which is needed, let me see if i can come up with a solution.

 

[stockholmicy]

I think you can use ISE core generator RAM-based shift Register to realize it. It's very precise and helpful. You don't need write any code but only need to instantiate it in your design. thank you.