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How to write testbench in VHDL?

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muni123

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Hello Everyone...
Can anyone suggest me how to write testbench in VHDL...
Can I use PLIs to verify a VHDL code? If it can be done in which book can I find proper stuff for working on it.

Thanks In Advance...
 

Guru59

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Re: Verification

Writing TestBenches using Functional HDL has Testbench Writing in VHDL....

I think...

Better go through that Book...
 

avimit

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    muni123

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muni123

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Re: Verification

Thank you very much avimit.
The URL you provided is so useful.
Thanks to Guru59 too....
 

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