How to write testbench in VHDL?

[muni123]

Hello Everyone...
Can anyone suggest me how to write testbench in VHDL...
Can I use PLIs to verify a VHDL code? If it can be done in which book can I find proper stuff for working on it.

Thanks In Advance...

 

[Guru59]

Re: Verification

Writing TestBenches using Functional HDL has Testbench Writing in VHDL....

I think...

Better go through that Book...

 

[avimit]

Re: Verification

I will suggest, you go through some example testbenches in vhdl
Here are a couple of simple examples
http://www.vlsiip.com/vhdl/booth_mult.tb.vhdl
http://www.vlsiip.com/vhdl/arm_bist_tb.vhd

in vhdl world we dont use PLIs, we use what are called as FLIs
a guide on FLIs can be found here
**broken link removed**

Kr,
avi
http://www.vlsiip.com

 

[muni123]

Re: Verification

Thank you very much avimit.
The URL you provided is so useful.
Thanks to Guru59 too....

 

[avimit]

Re: Verification

Hi, you are welcome, that url is actually my personal web site
Kr,
Avi
http://www.vlsiip.com