Mar 23, 2010 #1 P prashanthaditya Junior Member level 3 Joined Jul 8, 2007 Messages 27 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,454 i want to implement an AND gate with a delay of 5 units in it. eg : and #(5) a1(out,in1,in2); but the synthesis tool is removing the gate delay how should i implement the same in synthesis way If i check the gate level netlist i see it implemented an LUT how should i take an AND gate which has 5 delay units in it.
i want to implement an AND gate with a delay of 5 units in it. eg : and #(5) a1(out,in1,in2); but the synthesis tool is removing the gate delay how should i implement the same in synthesis way If i check the gate level netlist i see it implemented an LUT how should i take an AND gate which has 5 delay units in it.