prashanthaditya
Junior Member level 3
i want to implement an AND gate with a delay of 5 units in it.
eg : and #(5) a1(out,in1,in2);
but the synthesis tool is removing the gate delay
how should i implement the same in synthesis way
If i check the gate level netlist i see it implemented an LUT
how should i take an AND gate which has 5 delay units in it.
eg : and #(5) a1(out,in1,in2);
but the synthesis tool is removing the gate delay
how should i implement the same in synthesis way
If i check the gate level netlist i see it implemented an LUT
how should i take an AND gate which has 5 delay units in it.
