generic shift register

[satyandra.sharad]

shall i use generic shift register as n samples delay element, if no then how can i write vhdl code for n samples delay element

 

[treqer]

process (main_clk_100meg)
begin
if (main_clk_100meg'event and main_clk_100meg = '1')
then
a_1<= a_0;
a_2<= a_1;
-----------------------------
a_n <= a_n-1;
end if;
end process ;

 

[TrickyDicky]

or even neater:

process(clk)
begin
  if rising_edge(clk) then
    a <= a(a'high-1 downto 0) & ip;
  end if;
end process;