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Generic error at Vivado Simulator, how to debug this?

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Full Member level 3
Nov 21, 2013
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Hello All,

I am trying to connect a complete cache (L1D + L1I + L2 + DDR3 Controller) into my custom core. Because I really need to understand the connections and logic behind it - I want to customize also the cache at some level in the future - I am connecting these IP blocks manually.

I am using Vivado 2018.3 + Vivado Simulator.

For caches I used the IP system_cache from Vivado and for DDR controller I used MIG. I interconnected these IPs to my core and I can synthesize and implement the design.
For simulation, I merged some example code from MIG into my own design at top level for simulation, but when I try to simulate I receive the following error:

ERROR: [VRFC 10-1537] value -1 is out of target constraint range 0 to 2147483647 [/wrk/2018.3/nightly/2018_12_06_2405991/packages/customer/vivado/data/ip/xilinx/system_cache_v4_0/hdl/system_cache_v4_0_vh_rfs.vhd:1538]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

When I look at the file system_cache_v4_0_vh_rfs.vhd line 1538, it refers to a very generic VHDL function:

function int_to_std(v, n : integer) return std_logic_vector is
    return std_logic_vector(to_unsigned(v, n));
  end function int_to_std;

So I cannot really see where the error occurs, because this function int_to_std can be called from anywhere basically. Also, the system_cache_v4_0_vh_rfs.vhd is a monster of 80k lines of code and should be seen as a black box, I suppose.

Any ideas of how to debug this? How could I know which signal is out of range and calling function int_to_std?

Well, I discovered that, while behavioral simulation does not work, simulation based on synthesis does. So I am working with this for now. Hopefully, looking at synthesis simulation, I can discover what is going on.

The arguments of "to_unsigned" are constrained to natural type (not negative). Obviously the function is called somewhere with negative argument, probably to some misconfiguration of the IP. By looking more thoroughly to the error messages, you should be able to determine why and where this happens.

Thanks for the Reply FvM. That´s my understanding as well.

Vivado behavioral simulation is not very verbose in this case, there is no other simulation info/warning/error message which can help me here. I tried to increase the verbosity, without success.

I have encountered similar errors in Modelsim functional simulation. If an initial range is defined correctly for normal operation but accidentally becomes negative during reset due to some derivation from other parameters. In that case simulation will fail but synthesis will be ok. I wonder if you have control on that otherwise the ip vendor is to blame.

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