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CLK Generic Routing Warning

KingMoshe

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Hi,
I have a "place & route design" warning as following:

66011008 WARNING - The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=i2c_master/CLK_FSM loads=11 clock_loads=4

How I fix that warning?

Thanks
 
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dpaul

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This is just a warning. If the the design is working in hardware you may ignore it.

Generally system clocks are routed using dedicated routing resources. The tools are intelligent enough to dedicate resources to such system clocks (that must reach to most parts of the design) from your RTL design.

How I fix that warning?

Is this an IP core or your own design?
I see this is an I2C clock and this clock need not reach to other parts of the design. If this is your design, then try manually inserting a global clock buffer to the I2C clock path.
 

KingMoshe

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This is just a warning. If the the design is working in hardware you may ignore it.

Generally system clocks are routed using dedicated routing resources. The tools are intelligent enough to dedicate resources to such system clocks (that must reach to most parts of the design) from your RTL design.

How I fix that warning?

Is this an IP core or your own design?
I see this is an I2C clock and this clock need not reach to other parts of the design. If this is your design, then try manually inserting a global clock buffer to the I2C clock path.
Thanks, but my design do not worked well and I see a lot of unexpected events in my logic.
 

dpaul

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Thanks, but my design do not worked well and I see a lot of unexpected events in my logic.

First things first. Did your perform thorough functional verification of your design via simulation?
i.e. do you have a testbench that exercises your design quite well?

If not it must be done asap without even thing about other design steps.
 

KingMoshe

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Thanks for your reaponse.

Just saw you wrote to me:

Is this an IP core or your own design?
I see this is an I2C clock and this clock need not reach to other parts of the design. If this is your design, then try manually inserting a global clock buffer to the I2C clock path.

How I insert a global clock buffer?

Regarding the testbench, I do not have a testbench yet.
 

barry

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Did you run timing analysis? Did you have any timing constraints? If it passed timing analysis, but you say 'it does not work well', then there must be a problem with your hardware.
 

dpaul

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@KingMoshe ,
Regarding the testbench, I do not have a testbench yet.
That means you do not even know if your design does what it is supposed to do.
So it does not make any sense to do PnR of a design which is not functionally verified.

Then I repeat again....
First things first. Did your perform thorough functional verification of your design via simulation?
i.e. do you have a testbench that exercises your design quite well?

If not it must be done asap without even thing about other design steps.
 
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KingMoshe

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@KingMoshe ,
Regarding the testbench, I do not have a testbench yet.
That means you do not even know if your design does what it is supposed to do.
So it does not make any sense to do PnR of a design which is not functionally verified.

Then I repeat again....
First things first. Did your perform thorough functional verification of your design via simulation?
i.e. do you have a testbench that exercises your design quite well?

If not it must be done asap without even thing about other design steps.
I already burn my design code to the fpga and I test it by oscilloscope and I see that everything looked good, I meant to the I2C communication between EEPROM and FPGA, but when I perform little changes in my code all the data line looks terrible and I don't find the reason why.. how testbench can help me in such a case?
 

dpaul

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The FPGA is the I2C master and the EEPROM is the slave. The EEPROM must be having the I2C registers which hold the data send from the FPGA before sending it out to the EEPROM memory.
What you can do is to imitate these EEPROM I2C slave registers in the test bench. Your I2C master can be the DUT. Your testbench can drive the I2C master transactions and monitor if correct data is received at the EEPROM I2C slave registers.
This testbench idea is solely made on the assumption that there is possibly a problem between i2c master and slave communication. At-least I would do it this way, rather than the painful and time-costly of using scopes on the PCB traces.
 

KlausST

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Hi,

just a guess:
You generated the I2C clock by clock dividers / counters, instead of generating clock_enable signals.

I assume the problem lies in your code. Thus I recommend to show your code.

Klaus
 

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