# [SOLVED]How to use shift in SystemVerilog ?

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#### Xenon02

##### Member level 5
Hello !
I've been trying to use the operator ">>>" or "<<<" as an arithmetic shift in SystemVerilog. But I do have a problem because in the examples I see on the internet it is usually one input adress for example i_a = 1001 and it is shifter by 3 bits like in the example "i_a >>> 3" But I want to use instead of a specific number another adress like i_b = 0001. And use it in this form "i_a >>> i_b" But I don't know if the program will convert i_b which is binary into decimal. Plus I had an instruction to make i_a and i_b a Two's Complement adresses. So I have to also make i_b not negative.

Also how does it look when we go to logic gates ? The i_b can be any value. So How many logic gates will it make to shift adress i_a ? Infinitely ? Because even if i_a is shifted to the moment it is "0000" or "1111" it can shift even 8 bits more and it will be still "0000" or "1111". I can't imagine how the program will work or how it will look like using logic gates.

Thanks for any help !

Code:
module shifter
(
input signed [3:0] dataa,
input [2:0] datab,
output signed [3:0] result
);

assign result = dataa  >>> datab;

endmodule

Code:
module shifter
(
input signed [3:0] dataa,
input [2:0] datab,
output signed [3:0] result
);

assign result = dataa  >>> datab;

endmodule

What if I had something like this :

Code:
module ashift_example1(i_a, i_b, o_arith_left);
parameter BITS = 4;
input  logic signed [BITS-1:0] i_a, i_b;
output logic signed [BITS-1:0] o_arith_left;
output logic [1:0] o_error;
// Blok opisujacy logike
always_comb
begin
// arytmetyczne przesuniecie o i_b bitow
//                 w lewo (w strone MSB)
o_arith_left = (i_a <<< i_b);
end
endmodule

if I had i_b = 1111 which is -1 will it give error ? or what will happen ?

Because in GTKwave if I had i_a = 1010 and i_b = 1111. Then it should be an error because then I hava a situation where I want to shift i_a by -1 bit.
bit in gtkwave it shows o_y = 0000 why ? Shouldn't it give an error ?

Verilog LRM specifies that the right operand of shift operation is always treated as unsigned, see clause 11.4.10. I understand this so that a signed binary shift count is converted to unsigned, but I'm not sure. Your result seems to confirm my interpretation.

The question is, what's your intention. If you want left shift with negative shift count interpreted as right shift, you need a comparison and an explicite right shift.

Verilog LRM specifies that the right operand of shift operation is always treated as unsigned, see clause 11.4.10. I understand this so that a signed binary shift count is converted to unsigned, but I'm not sure. Your result seems to confirm my interpretation.

The question is, what's your intention. If you want left shift with negative shift count interpreted as right shift, you need a comparison and an explicite right shift.

I wanted to check what will happen if the i_b will be negative like i_b = 1000 or i_b = 1111 etc.
And see what will gtkwave give in the output. At the end if you use my code you will see that when the i_b is negative the output is always o_arith_left = 0000. I don't know why. I thought it will give something like o_arith_left = xxxx. undifined output because the shifting bites are negative. Instead it always give o_arith_left = 0000 I don't know why.

You didn't yet review the language reference manual?
--- Updated ---

I see that Intel Quartus is implementing the operation according to LRM (IEEE Std 1800-2017) 11.4.10
A signed shift count is casted to unsigned

Code:
(
input signed [3:0] dataa,
input signed [2:0] datab,
output signed [3:0] result
);
assign result = dataa  <<< datab; Last edited:

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