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# Shift register error

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#### shahrilmajid

##### Newbie level 4
Hi, I was trying to run a shift register in VHDL and was suddenly stuck by this error. Here is my code. I unable to view an output

Code:
library ieee;
use ieee.std_logic_1164.all;

entity shreg is
port(  d: in std_logic;
clk : in std_logic;
rightnotleft : in std_logic; -- right 1 into q3 passing to q1
clr: in std_logic; -- right 0 into q3 passing to q1
q: inout std_logic_vector(3 downto 0));
end shreg;

architecture beh of shreg is

begin

process (clk,clr)
begin
if clr ='1' then
q<= "0000";
elsif  (clk'event and clk = '1' and rightnotleft ='1') then
q(3) <=d;
q(2 downto 0) <= q (3 downto 1);
elsif (clk 'event and clk = '1') and rightnotleft = '0' then
q(0) <=d;
q(3 downto 1) <= q (2 downto 0);
end if;
end process;

end beh;

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#### TrickyDicky

A few problems here:
why is Q an inout? it should only be an out.
technically you are missing signals from the sensitivity list. I think you should put the checks on "rightnotleft" to be inside the clock if branch.

The error displayed is likely due to the face you made Q an inout - make it purely an out.

##### Super Moderator
Staff member
I would wager they used inout because they had a problem with Q can't be read (when it was defined as an out). Most posters new to VHDL don't set their tools to compile to the 2008 standard.

If you use the older VHDL standard when you change Q to an out you can't read Q (Q on the right hand side of an assignment, in an if comparison, etc), what you do is create a signal (e.g. Q_int) and use that in your code and assign the port using Q <= Q_int;

#### barry

It’s also very bad form, if not downright illegal, to have two clk’event statements in one process.

#### TrickyDicky

Nothing illegal about it from a VHDL POV. Also, the OPs code is really just a single edge flop with a signal that changes behaviour. So a good synthesisor should just work with this code.

It is multiple clocks that cannot be used.

##### Super Moderator
Staff member
Well maybe it's not illegal, but it also looks like they are implementing a gated clock in an FPGA which is inadvisable.

#### FvM

##### Super Moderator
Staff member
The problem is caused by missing initilization of q inout port and possibly behavior of the antique simulation tool.

Make your life easier by changing q port type to buffer, or out with VHDL2008 setting, as suggested.
--- Updated ---

Specifically, you need to setup q to all 'Z' in simulation waveform to run the simulation with inout port. Otherwise the in signal is driven by the simulator, resulting in 'X'.

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