siva_7517
Full Member level 2
Hi,
I am using design compiler to do synthesis.
I am having a warning after doing the compile. The warning state there is a 1 potential problem in design.When i do a check_design there are alot of port is not connected.
Below is few warning that is given by design_compiler. i have no idea where i went wrong.
Information: There are 1 potential problems in your design. Please run 'check_design' for more information. (LINT-99)
Warning: In design 'stage1_2_0_DW01_add_4', port 'CI' is not connected to any nets. (LINT-28)
Warning: In design 'stage1_2_0_DW01_add_4', port 'CO' is not connected to any nets. (LINT-28)
I am using design compiler to do synthesis.
I am having a warning after doing the compile. The warning state there is a 1 potential problem in design.When i do a check_design there are alot of port is not connected.
Below is few warning that is given by design_compiler. i have no idea where i went wrong.
Information: There are 1 potential problems in your design. Please run 'check_design' for more information. (LINT-99)
Warning: In design 'stage1_2_0_DW01_add_4', port 'CI' is not connected to any nets. (LINT-28)
Warning: In design 'stage1_2_0_DW01_add_4', port 'CO' is not connected to any nets. (LINT-28)