Design compiler warning

[siva_7517]

Hi,

I am using design compiler to do synthesis.
I am having a warning after doing the compile. The warning state there is a 1 potential problem in design.When i do a check_design there are alot of port is not connected.
Below is few warning that is given by design_compiler. i have no idea where i went wrong.


Information: There are 1 potential problems in your design. Please run 'check_design' for more information. (LINT-99)



Warning: In design 'stage1_2_0_DW01_add_4', port 'CI' is not connected to any nets. (LINT-28)
Warning: In design 'stage1_2_0_DW01_add_4', port 'CO' is not connected to any nets. (LINT-28)

 

[beta0]

I guess there is counter in your design, this waring is found after maping your design to a designware
adder and when optimzation stage is finished,
this problem will disappear.
So I guess you'll don't need worry about that.

 

[siva_7517]

hi,

Yes, there is a counter in my design. Eventually, when i do a gate level simulation i cant get the correct output.