Ata_sa16
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Hi all,
I have a problem in layout design.
I have a capacitor in my schematic and when I start doing layout I do generate all from source.
I want to do "flatten" and modify the layout of that capacitor.
I do it and make new cell and save it.
Now, the problem is when I do this, layout and schematic does not match and it does not show the connection anymore. In the schematic, it is named mim_cap however in layout it is new cell.
how can I solve this problem ???
Thank you all for your time.
I have a problem in layout design.
I have a capacitor in my schematic and when I start doing layout I do generate all from source.
I want to do "flatten" and modify the layout of that capacitor.
I do it and make new cell and save it.
Now, the problem is when I do this, layout and schematic does not match and it does not show the connection anymore. In the schematic, it is named mim_cap however in layout it is new cell.
how can I solve this problem ???
Thank you all for your time.