ERC error in Layout cadence virtuoso

[saqib007]

I am facing some issue regarding ERC. i have design a layout of inverter using SMIC 180nmBCD PDK,. i have used high voltage device NLDMOS (nld40h_ckt and pld40h_ckt)
and i got an ERC error mentioned below.
There is NWHT i.e. HVBN layer associated with aforementioned transistor which is basically used for isolation purposes. According to SMIC this layer must be connected to drain of the NLDMOS and when i do so then i face ERC error " NWHT is not connecting to power net" as given in the figure below.

i want the expert's opinion on this matter if whether I can ignore this ERC or there is any solution does exist for it. I expect high voltage layout engineer will present their opinion.

 

[dick_freebird]

Drain of NLDMOS as shown, does not want to be tied to a power
net. So doing would ruin anything but a source follower.

The HV PMOS will need to sit in a HV NWell and that wants a N+ ring.

The layout appears to have concentric guardrings. You might have to
connect them individually to opposing rails, according to "hidden"
net connection properties. I recommend you find proper cross sections
so you can understand the isolation scheme, which can be complex and
"fussy" when you have to deal with junction isolation on flying high
voltages (and faults).

 

[saqib007]

Drain of NLDMOS as shown, does not want to be tied to a power
net. So doing would ruin anything but a source follower.

The HV PMOS will need to sit in a HV NWell and that wants a N+ ring.

The layout appears to have concentric guardrings. You might have to
connect them individually to opposing rails, according to "hidden"
net connection properties. I recommend you find proper cross sections
so you can understand the isolation scheme, which can be complex and
"fussy" when you have to deal with junction isolation on flying high
voltages (and faults).

Thank you for your answer but let me clear few things:
1) We are not talking about connecting drain of NLDMOS to power net rather we are talking to whether connect HVBN (which is an isolation layer of HV devices) to the drain of NLDMOS or to power net. By default every NLDMOS has HVBN layer and by default it should be connected to the drain of the associated NLDMOS and when we do so then we get an ERC error as shown in the pictures. So the question is that can we ignore this ERC? if not, then what is the solution?
2) And yes we have studied the cross section in details the HVBN layer of NLDMOS must be connected to potential higher than that of the substrate. the substrate of our design is connected to ground so if we connect HVBN layer to the drain of NLMDMOS (as also required by default) then it should work because the intrinsic diodes will be in off state. but agian when we do so then we face ERC error, i am wondering that why this ERC happens?

 

[dick_freebird]

You might inspect the code for that particular rule (if it is not
hidden from your view) and look for "special logic" involving
recognition layers or whether the feature coincides with a
particular device "tag". When rules "get modal" with specific
rules attending specific devices, there should be some and
its formulation will point to "what's required".

Of course if your foundry*tool_vendor insists to encrypt every
bit of technology detail, you may just be screwed.

 

[saqib007]

You might inspect the code for that particular rule (if it is not
hidden from your view) and look for "special logic" involving
recognition layers or whether the feature coincides with a
particular device "tag". When rules "get modal" with specific
rules attending specific devices, there should be some and
its formulation will point to "what's required".

Of course if your foundry*tool_vendor insists to encrypt every
bit of technology detail, you may just be screwed.

thank you once again for your help