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Basic question...confusing me....

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Guru59

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Can any one explain the functionality of "&&" operator....

for example:::

a = 1010
b = 0001

then what is the value of " a && b " .....


Thanks
 

santoshl

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hey, its very simple.
single &, | represent bitwise operators. while double & ,| ( ie && , || ) represents logical operators.

o/p of logical operators is a single bit. i.e. 1 (if true, non-zero) or 0 (if false , zero).
In ur case both "a" and "b" are non zero, hence the o/p is TRUE (in digital terminology it is 1 )

Hope it helped u.

If the queston was a&b, then ans is 0000
 

xlxlyu

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it seems like logic operator,&& is AND .
so if a or b is zero,the ans is 0.
if both a and b are not zero ,the ans is 1.
 

jkang

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The && operator is only 2-state. It is either 1 or 0 depending on the operands.

The & operator is 4-state. It can be 1, 0, X or Z depending on the operands.

&& is called a logical operator because both sides need to be 1 in order for the output to be 1. In all other cases, it is 0. So if you had a = 0010 and b = 0110,

a && b would give you 0 (or compile error depending on your synthesizer).

A better (and proper) way to use && would be:

(a == 0010 && b == 0110)

& is a bitwise operator because it takes the bitwise AND of both operands.

So, a & b would result in 0010.
 

lordsathish

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hey is'nt && operator concantenation operator in vhdl and verilog...
a="1010";
b="0001";
then "a && b" must be "10100001"...

hope i'm right... correct me if i'm wrong...
 

carv_13

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concatenation in verilog is done is using braces {} with , seperating the objects to be concatenated. && is used for bitwise ANDing.
 

lordsathish

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& operator is used for concatenation in vhdl:D:D:D:D
 

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