Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

anyone have ideas about the memory design in silicon ensembl

Status
Not open for further replies.

shiningblue

Newbie level 6
Joined
Jan 25, 2005
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
USA
Activity points
92
I use ARTISAN to generate RAM, and get the LEF file. But it doesn't work well.

The tool is silicon ensemble. I import the LEF file of cell library first, and then import the LEF file of memory, It always said "Invalid token here OR missing space between token and ":""

It drives me crazy.
 

aravind

Advanced Member level 1
Joined
Jun 29, 2004
Messages
487
Helped
45
Reputation
94
Reaction score
18
Trophy points
1,298
Location
india
Activity points
3,597
how did u generate RAM using Artisan.
Artisan gave any tool for generating RAM.
or r u using synopsys memory compiler?
 

zhustudio

Advanced Member level 4
Joined
Jul 15, 2002
Messages
102
Helped
8
Reputation
16
Reaction score
2
Trophy points
1,298
Location
China
Activity points
1,049
Please check your LEF file version. SE does not recognize high version of LEF 5.5 5.6, 5.4(not sure).
And check the LEF file, the space need to be added in front of ';' in each line
 

shiningblue

Newbie level 6
Joined
Jan 25, 2005
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
USA
Activity points
92
Re: anyone have ideas about the memory design in silicon ens

Thanks for the reply

ARTISAN has the memory generator which can generate SRAM, ROM and Registerfile

Added after 2 minutes:

zhustudio said:
Please check your LEF file version. SE does not recognize high version of LEF 5.5 5.6, 5.4(not sure).
And check the LEF file, the space need to be added in front of ';' in each line

The version of LEF file of memory is 5.2, which should be able to be run at silicon ensemble.

also the space has been added in front of ';' in each line

anyone has any ideas?
 

erixlion

Junior Member level 1
Joined
Jul 2, 2006
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,404
Re: anyone have ideas about the memory design in silicon ens

Hi
I am using CCAR, (Cadence chip assembly router) in Solaris 8, with ic4.46, but the lic dosent work so I am getting SILICON ENSEMBLE, or GATE ENSEMBLE instead.

I found the keys in my current license.dat for SILICON ENSEMBLE and GATE ENSEMBLE, but I dont know where can I download them, anyone got idea?

I can exchange everything I have for this software even though you just tell me a download link that works.

I have: IC5141, IC5033, ASSURA, CALIBRE 2006(UNIX), CALIBRE 2005(LINUX + UNIX) CALIBRE 2004, TSMC .25UM, 0.18UM, LEDIT 11.1, and many more include tutorial books.........

all are cracked working version (or have working lic.).
just name it what you want. let me know : gpsfan#gmail.com
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top