entity mc_proj_v11 is
Port ( clock : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (3 downto 0);
data_out : out STD_LOGIC_VECTOR (15 downto 0);
count_out : out STD_LOGIC;
sel : in STD_LOGIC_VECTOR (1 downto 0));
end mc_proj_v11;
architecture Behavioral of mc_proj_v11 is
signal data_out_sig:std_logic_vector(15 downto 0):="0000000000000000";
signal count_out_sig:std_logic:='0';
begin
process(clock,data_in)
begin
if clock'event and clock='1' then
data_out_sig <= data_in &'0'&'0'&'0'&'0'&'0'&'0'&'0'&'0'&'0'&'0'&'0'&'0';
case sel is
when "01" => data_out_sig <= (data_out_sig srl 4) & data_in;
when "10" => data_out_sig <= (data_out_sig srl 8) & data_in;
when "11" => data_out_sig <= (data_out_sig srl 12) & data_in;
when others => data_out_sig<="0000000000000000";
end case;
end if;
end process;
process(clock)
begin
if clock'event and clock='1' then
data_out_sig<=data_out_sig - 1;
if (data_out_sig<="0000000000000000") then
count_out_sig<='1;
else
count_out_sig<='0';
end if;
end process;
data_out<=data_out_sig;
count_out<=count_out_sig;
end Behavioral;
entity mc_proj_v11 is
Port ( clock : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (3 downto 0);
data_out : out STD_LOGIC_VECTOR (15 downto 0);
count_out : out STD_LOGIC;
sel : in STD_LOGIC_VECTOR (1 downto 0));
end mc_proj_v11;
architecture Behavioral of mc_proj_v11 is
signal data_out_sig:std_logic_vector(15 downto 0):="0000000000000000";
signal count_out_sig:std_logic:='0';
begin
process(clock,data_in)
begin
if (rising_edge(clk)) then
case sel is
when "01" => -- 8 bits are valid
data_out_sig <= x"00" & data_out_sig(3 downto 0) & data_in;
when "10" => -- 12 bits are valid
data_out_sig <= x"0" & data_out_sig(7 downto 0) & data_in;
when "11" => -- 16 bits are valid
data_out_sig <= data_out_sig(11 downto 0) & data_in;
when others =>
data_out_sig <= x"0000";
end case;
end if;
end process;
-- process(clock)
-- begin
-- if (rising_edge(clk)) then
-- data_out_sig<=data_out_sig - 1;
-- if (data_out_sig<="0000000000000000") then
-- count_out_sig<='1;
-- else
-- count_out_sig<='0';
-- end if;
-- end process;
data_out<=data_out_sig;
count_out<=count_out_sig;
end Behavioral;
I select 10
Data_out_sig<--- data_in(3 downto 0) & data_in(3 downto 0) & data_in(3 downto 0);
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