How to extract input/reg size in Verilog?

[adamira]

Hi,
VHDL has a powerful feature called attributes. Using attribute I can generalize modules quite easily, for example:

entity alaram is
port(
 clk : in std_logic;
 reset : in std_logic;
 CountTo : in std_logic_vector;
 CountEn : in std_logic;
 Done : out std_logic);
end alaram ;

architecture arch of alaram is
    signal counter : std_logic_vector(CountTo'range);
begin
  process(clk) begin
    if (reset='1') then
      counter <= (others => '0');
      Done <= '0';
    elsif (rising_edge(clk)) then
      if (CountEn='1') then
        if (counter = CountTo) then
          Done <= '1';
          counter <= (others => '0');
        else
          Done <= '0';
          counter <= counter + '1';
        end if;
      end if;
    end if;
  end process;
end arch;

The counter in this module get its size using an attribute, and match its size to the "CountTo" input size. More importantly "CountTo" input can be any size...

I couldn't find an equivalent Verilog syntax. Not to the counter size being generic and not to the input being generic.
Passing a parameter is not the solution I am looking for because in complicated blocks there might be dozens of attributes and I don't want to pass too many parameters or create dozens of local parameters...

Are you familiar with an equivalent Verilog syntax?
Thanks

 

[FlyingDutch]

Hello,

you have three options:
1) define
2) parameters
3) localparam

Here is link related to parameters:

https://www.chipverify.com/verilog/verilog-parameters

regards

 

[adamira]

Thank you,
So like I thought, there is not a exact equivalent.. Eventually you'll have to create another code instance (define/param/local param) to support generic code.

What if simply want to do something like:

reg [10:0] long;
reg [5:0] short;

//imagine always block:
short <= long[short:0] //NOT WORKING - searching for working syntax

I might change short size from time to time and I want to change it only in the declaration area...

 

[FvM]

Your example has nothing to do with the above VHDL attribute usage, where the actual signal width in the instantiation is reported by the attribute. Variable width must be fixed at synthesis time and can't be modified by another variable, only by a static parameter.

A width parameter set in the module instantiation is the next best equivalent to the VHDL method.

 

[adamira]

The input variable width part of the example indeed has nothing to do with VHDL attribute, but this feature together with the VHDL attribute used later when declaring the counter signal, creates generic module without passing any additional information. (the compiler will auto-generate all the necessary information, like actual port width)

I understand that Verilog relies on passing parameter for this kind of behavior.

But what about in-module "attributes"? What the Verilog next best equivalent for those? see my second example:

reg [10:0] long;
reg [5:0] short;
//imagine always block:
short <= long[short:0] //NOT WORKING - searching for working syntax

 

[FvM]

Attributes are reading parameters of objects, not setting it. You have similar system functions in SystemVerilog like $size, $left etc. But SystemVerilog doesn't provide unconstraint module ports like VHDL, so the post #1 example has to implemented slightly different, e.g. using parameters.

In post #3, you are apparently trying variable length array select, which isn't directly possible. Can be however achieved with bitwise operations. Technically it's a kind of mux or variable bitmask.

 

[adamira]

Attributes are reading parameters of objects, not setting it. You have similar system functions in SystemVerilog like $size, $left etc. But SystemVerilog doesn't provide unconstraint module ports like VHDL, so the post #1 example has to implemented slightly different, e.g. using parameters.

Thank you, that sums it up.

In post #3, you are apparently trying variable length array select, which isn't directly possible. Can be however achieved with bitwise operations. Technically it's a kind of mux or variable bitmask.

I meant something much simpler. just to select the "short" reg range.
I know how to code it using local parameter:

localparam SHORT_LEN = 6;
reg [10:0] long;
reg [SHORT_LEN-1:0] short;
//imagine always block:
short <= long[SHORT_LEN-1:0] //WORKING!

But I don't want to create local parameter... In VHDL I could use attribute like so:
short <= long[short'left downto 0]
or
short <= long[short'range]

 

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Code Verilog - [expand]
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reg [10:0] long;
reg [5:0] short;
// in an always block you would use
short <= long; // assigns short[5:0] with long[5:0] truncating long[10:6] (Note: gives a synthesis warning about widths not matching)

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