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[SOLVED] 12 bit input using only 4 input line......

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here your sel is 10, so its its 12 bits valid operation, so you need to pass the inputs in the consecutive three cycles.
so in the first clock cycle say if you are passing the data_in as x"F", the below thing will execute as
data_out_sig <= x"0" & data_out_sig(7 downto 0) & data_in;
here after the 1st clock (means the beginning of the 2nd clock) the data_out_sig bwcomes x"000F"
in the 2nd clock cycle say if you are passing the data_in as x"3", the below thing will execute as
data_out_sig <= x"0" & data_out_sig(7 downto 0) & data_in;
here after the 2nd clock (means the beginning of the 3rd clock) the data_out_sig bwcomes x"00F3"
in the 3rd clock cycle say if you are passing the data_in as x"7", the below thing will execute
data_out_sig <= x"0" & data_out_sig(7 downto 0) & data_in;
here after the 3rd clock (means the beginning of the 4th clock) the data_out_sig bwcomes x"0F37"

I think its better to add a reset port and an enable port to your design
 

imbichie said:
here your sel is 10, so its its 12 bits valid operation, so you need to pass the inputs in the consecutive three cycles.
so in the first clock cycle say if you are passing the data_in as x"F", the below thing will execute as
data_out_sig <= x"0" & data_out_sig(7 downto 0) & data_in;
here after the 1st clock (means the beginning of the 2nd clock) the data_out_sig bwcomes x"000F"
in the 2nd clock cycle say if you are passing the data_in as x"3", the below thing will execute as
data_out_sig <= x"0" & data_out_sig(7 downto 0) & data_in;
here after the 2nd clock (means the beginning of the 3rd clock) the data_out_sig bwcomes x"00F3"
in the 3rd clock cycle say if you are passing the data_in as x"7", the below thing will execute
data_out_sig <= x"0" & data_out_sig(7 downto 0) & data_in;
here after the 3rd clock (means the beginning of the 4th clock) the data_out_sig bwcomes x"0F37"

I think its better to add a reset port and an enable port to your design
Click to expand...

@ imbichie thank you :) I understood how it works :]
Now Trying to write the code hope I can write working code :}
Regards
 

Hi i wrote the code but its showing error
# ** Error: down_counter_v11.vhd(60): No feasible entries for infix op: "=".
# ** Error: down_counter_v11.vhd(60): near "=": expecting: ')'
# ** Error: down_counter_v11.vhd(68): near "=": expecting: ')'
# ** Error: down_counter_v11.vhd(77): near "=": expecting: ')'
# ** Error: down_counter_v11.vhd(85): near "=": expecting: ')'
# ** Error: C:/Modeltech_5.8b/win32/vcom failed.
here is my code-- Please help with this. i have only less time left to complete this :(
Code: 
entity down_counter_v11 is
    Port ( reset : in  STD_LOGIC;
           clock : in  STD_LOGIC;
           load : in  STD_LOGIC;
           enable : in  STD_LOGIC;
           data_in : in  STD_LOGIC_VECTOR (3 downto 0);
           data_out1 : out  STD_LOGIC_VECTOR (3 downto 0);
           count_out : out  STD_LOGIC;
           rxin : in  STD_LOGIC;
           rxout : out  STD_LOGIC;
           txin : in  STD_LOGIC;
           txout : out  STD_LOGIC;
           data_out2 : out  STD_LOGIC_VECTOR (7 downto 0);
           data_out3 : out  STD_LOGIC_VECTOR (11 downto 0);
           data_out4 : out  STD_LOGIC_VECTOR (15 downto 0));
end down_counter_v11;

architecture Behavioral of down_counter_v11 is
signal data_out1_sig:std_logic_vector(3 downto 0);
signal data_out2_sig:std_logic_vector(7 downto 0);
signal data_out3_sig:std_logic_vector(11 downto 0);
signal data_out4_sig:std_logic_vector(15 downto 0);
signal count_out_sig:std_logic:='0';
signal r:std_logic:='0';
signal t:std_logic:='0';
begin
	process(clock)
		begin
			if (clock'event and clock='1') then 
					elsif (load = '0' & enable = '0') then
						data_out1_sig<=data_in;
						data_out1_sig<=data_out1_sig-1;
					if data_out1_sig="0000" then
							count_out_sig<='1';
					else
							count_out_sig<='0';
					end if;
				elsif (load = '0' & enable ='1') then
						data_out2_sig<=x"00" & data_out2_sig(3 downto 0) & data_in;
						data_out2_sig<=data_out2_sig-1;
					if data_out2_sig="00000000" then
							count_out_sig<='1';
						else
							count_out_sig<='0';
					end if;
	
			elsif (load ='1' & enable ='0') then
					data_out3_sig<=x"0" & data_out3_sig(7 downto 0) & data_in;
					data_out3_sig<=data_out3_sig-1;
					if data_out2_sig="000000000000" then
							count_out_sig<='1';
						else
							count_out_sig<='0';
					end if;	
			elsif (load='1' & enable='1') then
					data_out4_sig<=x"00" & data_out4_sig(11 downto 0) & data_in;
					data_out4_sig<=data_out4_sig-1;
					if data_out2_sig="0000000000000000" then
							count_out_sig<='1';
						else
							count_out_sig<='0';
					end if;
	end if;
end process;
data_out1<=data_out1_sig;
data_out2<=data_out2_sig;
data_out3<=data_out3_sig;
data_out4<=data_out4_sig;
count_out<=count_out_sig;
r<=rxin;
t<=txin;
rxout<=r;
txout<=t;
end Behavioral;

P.S. rxin rxout are meant for some connection in the pcb board which is mandatory so please omit them :)
Regards
 

have you included the ieee std libraries

- - - Updated - - -

process(clock)
begin
if (clock'event and clock='1') then
elsif (load = '0' & enable = '0') then

here no need of elsif instead of this you must starts with if and close the first if at the end of all the if and elsif statement

- - - Updated - - -

Code: 
entity down_counter_v11 is
    Port ( reset : in  STD_LOGIC;
           clock : in  STD_LOGIC;
           load : in  STD_LOGIC;
           enable : in  STD_LOGIC;
           data_in : in  STD_LOGIC_VECTOR (3 downto 0);
           data_out1 : out  STD_LOGIC_VECTOR (3 downto 0);
           count_out : out  STD_LOGIC;
           rxin : in  STD_LOGIC;
           rxout : out  STD_LOGIC;
           txin : in  STD_LOGIC;
           txout : out  STD_LOGIC;
           data_out2 : out  STD_LOGIC_VECTOR (7 downto 0);
           data_out3 : out  STD_LOGIC_VECTOR (11 downto 0);
           data_out4 : out  STD_LOGIC_VECTOR (15 downto 0));
end down_counter_v11;

architecture Behavioral of down_counter_v11 is
signal data_out1_sig:std_logic_vector(3 downto 0);
signal data_out2_sig:std_logic_vector(7 downto 0);
signal data_out3_sig:std_logic_vector(11 downto 0);
signal data_out4_sig:std_logic_vector(15 downto 0);
signal count_out_sig:std_logic:='0';
signal r:std_logic:='0';
signal t:std_logic:='0';
begin
	process(clock)
		begin
			if (clock'event and clock='1') then 
				if (load = '0' & enable = '0') then
                    data_out1_sig<=data_in;
                    data_out1_sig<=data_out1_sig-1;
                    if data_out1_sig="0000" then
                        count_out_sig<='1';
                    else
                        count_out_sig<='0';
                    end if;
				elsif (load = '0' & enable ='1') then
					data_out2_sig<=x"00" & data_out2_sig(3 downto 0) & data_in;
					data_out2_sig<=data_out2_sig-1;
                    if data_out2_sig="00000000" then
						count_out_sig<='1';
					else
						count_out_sig<='0';
                    end if;
                elsif (load ='1' & enable ='0') then
                    data_out3_sig<=x"0" & data_out3_sig(7 downto 0) & data_in;
                    data_out3_sig<=data_out3_sig-1;
                    if data_out2_sig="000000000000" then
                        count_out_sig<='1';
                    else
                        count_out_sig<='0';
                    end if;	
                elsif (load='1' & enable='1') then
                    data_out4_sig<=x"00" & data_out4_sig(11 downto 0) & data_in;
                    data_out4_sig<=data_out4_sig-1;
                    if data_out2_sig="0000000000000000" then
                        count_out_sig<='1';
                    else
                        count_out_sig<='0';
                    end if;
                end if;
            end if;
end process;
data_out1<=data_out1_sig;
data_out2<=data_out2_sig;
data_out3<=data_out3_sig;
data_out4<=data_out4_sig;
count_out<=count_out_sig;
r<=rxin;
t<=txin;
rxout<=r;
txout<=t;
end Behavioral;

i think this will solve, i havent simulate it
 

you cannot use & in an if. & is the concatenate operator, not the AND operator. So in your if/elsif statements you're building a vector of two booleans (which makes no sense)

you mean:

elsif load = '1' and enable = '1' then
 

TrickyDicky said:
you cannot use & in an if. & is the concatenate operator, not the AND operator. So in your if/elsif statements you're building a vector of two booleans (which makes no sense)

you mean:

elsif load = '1' and enable = '1' then
Click to expand...

Thanks trickydicky :)
Regards

- - - Updated - - -

@ imbichie.
Ok now got no errors and successfully loaded into fpga but its not doing the job :I :I
 

@ imbichie
hi
I had no time to check simulation results yesterday.. Probably I'm going to check now.
Regards

- - - Updated - - -

Simulation is not right!! its not doing what I need!!:roll::cry:
 

Pavithra89 said:
Simulation is not right!! its not doing what I need!!:roll::cry:
Click to expand...

Simulation is not right means. What is wrong in it ? means is the code is wrong with functionality or its not simulating ?

Have you written the testbench for it ?

Also have you corrected one thing below

if (clock'event and clock='1') then
elsif (load = '0' & enable = '0') then

here it should be like this only

if (clock'event and clock='1') then
if (load = '0' and enable = '0') then
 

@ imbichie
Hi
After continuously trying and some changes in the code I got simulation working right :D :D :D
But getting xst error :[
sequential logic for node <data_reg> appears to be controlled by multiple clocks
Regards
 

But getting xst error :[
sequential logic for node <data_reg> appears to be controlled by multiple clocks
Click to expand...
Sounds plausible. You have already shown non-synthesizable constructs in previous posts, e.g. in post #24
Code: 
if (clock'event and clock='1') then 
elsif xxx then
elsif yyy then
end if;

You need to refer to the well known template for hardware register modelling:

Code: 
if <asynchronous condition1> then

[elsif  <asynchronous condition2> then] -- optional, not well supported by some FPGA hardware

elsif <clock edge sensitive event>

end if;
There can't be more than one clock edge sensitive event.
 
Thanks that was the error!! corrected them now Im getting the output in hardware as well :)

- - - Updated - - -

I'm thankful to all who helped me
Thanks alot!
Regards
 

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