[SOLVED] 12 bit input using only 4 input line......

[Pavithra89]

Hi
I want to write a vhdl code for down counter which is like if I select 01 it should take 8 bits as input and if i select 10 it should take 12 as input but using only 4 input lines. Is there any way to perform this? If so please help me :}
Regards

P.S. depending upon the input data size it performs down counter.. How is this possible? Guide me in this asap :}

 

[TrickyDicky]

Yes it is possible. WHy not post the code you have already and we can help with any problems.

 

[Pavithra89]

Hi
Before I write a code, I have a doubt,
How will I store the value of first input bits, i.e., 4 bits and next four bits and so on to separate buffer or whatever, So that I concatenate them later to get resulting 12 bits.

P.S.Excuse me for my newbie questions :/

 

[FvM]

Being new to logic programming is no justification for not asking clear questions. Apparently you intend to transmit data in 4-Bit nibbles serially. How about sketching a timing diagram of the involved waveforms? There must be a clock or similar.

 

[Pavithra89]

Hi
Let me explain clearly,
I got only four input data lines to my FPGA which are inputs (starting number(or bits) from where counter starts down counting) to programmable down counter program block in FPGA. So it is like i can only perform 4 bit programmable down counter.
Since I want to employ even 8 bit, 12-bit and even 16-bit counter using only those four input lines or pins i can say
I wanted to know how can I use those four pins to send 8,12,16 bit data.
That is, I need how to write a code where I can send 4 bits store it to buffer1/register1, then send other 4 bits store them to buffer2, then concatenate them to get 8-bit data to programmable down counter. :-?
Regards

 

[TrickyDicky]

Sounds like you're getting there

 

[Pavithra89]

getting what and where :shock:

 

[TrickyDicky]

you already said you could store the input in a register or two (like a shift register) that you can then concatenate when you have enough bits. You'll just need some way of telling the design how many words to shift in.

 

[Pavithra89]

But I have a doubt how will FPGA accept its input--> 3 4-bit input or 2 4-bit input.. I'm really confused :-|

 

[mrflibble]

That's okay. Confusion and doubt are all part of the human condition.

I think what you are looking for is a shift register that takes a 4 bit input, and has a (max) 16 bit output. If yes, best start coding. If not, please post clear requirements. And if part of your confusion comes from having to handle a variable word size like "8,12,16 bit data" as you say ... then how about the following:

The first 4 bits you send is ALWAYS meant to signal how many 4-bit nibbles are coming up next.

I would use:
0 ==> clever reset circuit
1 ==> reserved for when you might want 4 bit data as well
2 ==> 8 bit data
3 ==> 12 bit data
4 ==> I am sure you detect the pattern by now
5 ==> no I don't have vhdl code for that

And after this first word you simply clock on the 4-bit nibbles to form your 8, 12, or 16 bit data word. Hope that helps.

Edit: some example data ... Suppose you want to send 8 bits = 0xC0, followed by 16 bits = 0xFFEE. Then you would send the following nibbles: 0x2, 0xC, 0x0, 0x4, 0xF, 0xF, 0xE, 0xE. Where the stuff in bold is the start of transfer that tells you what size the transfer is.

 

[Pavithra89]

Aww thank u...
I think my confusion reduced to some extent
I need sample code as to how to tell FPGA as to how many bits of word coming :roll:
Google doesn't have answer for that though :{

 

[barry]

I think mrfribble already gave you a solution. Just to possibly confuse you more, here's another idea: You ALWAYS send four, 4-bit nybbles. If you want an 8-bit counter down counter, then the upper 2 nybbles you send are all zero.

 

[Pavithra89]

hi again
After some careful study of my pcb board ,I observed that there are two more pins are available so thought why not I use them to tell FPGA how many bits I'm going to send.
Say 01--> 8 bits;
10--> 12 bits; probably using case statement
My present status is I've written the code :}:-? and it has got some errors, trying to rectify them

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Confused

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This is my code so far

entity mc_proj_v11 is
    Port ( clock : in  STD_LOGIC;
           data_in : in  STD_LOGIC_VECTOR (3 downto 0);
           data_out : out  STD_LOGIC_VECTOR (15 downto 0);
           count_out : out  STD_LOGIC;
           sel : in  STD_LOGIC_VECTOR (1 downto 0));
end mc_proj_v11;
architecture Behavioral of mc_proj_v11 is
signal data_out_sig:std_logic_vector(15 downto 0):="0000000000000000";
signal count_out_sig:std_logic:='0';
begin
process(clock,data_in)
	begin
		if clock'event and clock='1' then
			data_out_sig <= data_in &'0'&'0'&'0'&'0'&'0'&'0'&'0'&'0'&'0'&'0'&'0'&'0';
			case sel is
				
				when "01" => data_out_sig <= (data_out_sig srl 4) & data_in;
				
				when "10" => data_out_sig <= (data_out_sig srl 8) & data_in;
				
				when "11" => data_out_sig <= (data_out_sig srl 12) & data_in;
				
				when others => data_out_sig<="0000000000000000";
			end case;
		end if;
end process;

process(clock)
	begin
	if clock'event and clock='1' then
		data_out_sig<=data_out_sig - 1;
		if (data_out_sig<="0000000000000000") then
				count_out_sig<='1;
			else
				count_out_sig<='0';
		end if;
end process;
data_out<=data_out_sig;
count_out<=count_out_sig;
end Behavioral;

 

[imbichie]

Hi Pavithra89,

When i looked your code, one thing initially i noticed that there are multiple assignments to the signal data_out_sig in both the process, that causes an error.

 

[Pavithra89]

@imbichie
Hmmmm yeah!
And even srl doesn't seem to get along with. It says invalid operator! maybe because of vector-logic incompatibility
Thanks

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@mrfribble
What instructions should I use to tell FPGA as to how many 4 bits am going to send!!!

 

[imbichie]

Hi Pavithra89,

I haven't gone through the entire replys, from my understanding
you have 4 input data_in and you have 16 output data_out
with respect to the select line sel you need to config the data_out as 8, 12, 16 bits
i just wants to know , let if the sel is "10" means 12 bit data_out selection;
then are you passing the MSB (data_out(11 downto 8)) first or the LSB (data_out(3 downto 0)) first
for eg:
if you need the data_out as X"0F37"
whether you are passing the first data_in as X"7", then X"3" then X"F" (LSB first)
or X"F" then X"3" then X"7" means MSB First

 

[TrickyDicky]

srl/sll are not defined for std_logic_vector. You need to use signed or unsigned type instead.

 

[Pavithra89]

@ imbichie
I'm sending MSB data out first , that is what Im asked to do . Im really confused. The code which is not working
Thanks

 

[imbichie]

entity mc_proj_v11 is
    Port ( clock : in  STD_LOGIC;
           data_in : in  STD_LOGIC_VECTOR (3 downto 0);
           data_out : out  STD_LOGIC_VECTOR (15 downto 0);
           count_out : out  STD_LOGIC;
           sel : in  STD_LOGIC_VECTOR (1 downto 0));
end mc_proj_v11;
architecture Behavioral of mc_proj_v11 is
signal data_out_sig:std_logic_vector(15 downto 0):="0000000000000000";
signal count_out_sig:std_logic:='0';
begin
process(clock,data_in)
	begin
		if (rising_edge(clk)) then
			case sel is
				when "01" => -- 8 bits are valid
                    data_out_sig <=  x"00" & data_out_sig(3 downto 0) & data_in;
                
				when "10" => -- 12 bits are valid
                    data_out_sig <= x"0" & data_out_sig(7 downto 0) & data_in;
				
				when "11" => -- 16 bits are valid
                    data_out_sig <= data_out_sig(11 downto 0) & data_in;
				
				when others => 
                    data_out_sig <= x"0000";
			end case;
		end if;
end process;

-- process(clock)
	-- begin
	-- if (rising_edge(clk)) then
		-- data_out_sig<=data_out_sig - 1;
		-- if (data_out_sig<="0000000000000000") then
				-- count_out_sig<='1;
			-- else
				-- count_out_sig<='0';
		-- end if;
-- end process;
data_out<=data_out_sig;
count_out<=count_out_sig;
end Behavioral;

Is this is the thing you wanted, i don't know what is the relevance of count_out here.

the other parts will work i think.

i hvan't compiled it, so may be some errors will be there, but it will helps to avoid the srl and may give some idea

 

[Pavithra89]

Hi Thanks alot.
Serioulsy Im waiting for one such help
Im even designing presettable down counter where the presettable value are those 8 or 12 bits data :} So count_out is here
Let me try this and let you know.
Regards

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@ imbichie
I have a question
In each case data_out_sig takes different value or it remains the same?
How does parallel loading new value affect previous input bits.
Say I need 12 bit output

I select 10
Data_out_sig<--- data_in(3 downto 0) & data_in(3 downto 0) & data_in(3 downto 0);

I have to load three new values of data_in. Should I use some condition or the same code works?? I'm really confused!!! Please help! Give me some suggestion. I dont mind if you screw me up for asking newbie question but I need the answer