kvnsmnsn
Junior Member level 1
I am at a loss as to why my piece of Verilog code isn't working. The general idea of my code is that I have up to six queues, three "down" and three "up," and given a side (determined by value (loadingUp)), I'm trying to find which queue on that side has the least value at its head. My testbench passes (2'b10) and (2'b00) into values (hdUm) and (hdDm) respectively in my (sPivots) module. But if I immediately assign debugging values (d_hdUm) and (d_hdDm) respectively to those two inputs and return them as outputs, I get a value of (zz) for each of them. I checked my Verilog (that I'm attaching), and I don't do anything with (hdUm) or (hdDm) except pass them as inputs into my (MuOuNmx) module. How are these two values getting changed? Any pointers on this would be greatly appreciated.
My (sPivots) module (with all the modules it uses inserted) is:
My testbench is:
And the results when I run this on EDA Playground are:
Please let me know if you can see anything that I'm doing wrong.
Never mind! I figured out what I was doing wrong.
My (sPivots) module (with all the modules it uses inserted) is:
Code:
// (c) Kevin Simonson 2025
module Nt ( output rslt
, input op);
supply0 ground;
supply1 power;
nmos n( rslt, ground, op);
pmos p( rslt, power , op);
endmodule
module Nd2 ( output rslt
, input aOp
, bOp);
supply0 ground;
supply1 power;
wire srCn;
nmos na( srCn, ground, aOp);
nmos nb( rslt, srCn , bOp);
pmos pa( rslt, power , aOp);
pmos pb( rslt, power , bOp);
endmodule
module Nr2 ( output rslt
, input aOp
, bOp);
supply0 ground;
supply1 power;
wire srCn;
nmos na( rslt, ground, aOp);
nmos nb( rslt, ground, bOp);
pmos pa( srCn, power , aOp);
pmos pb( rslt, srCn , bOp);
endmodule
module Nmx2 ( output rslt
, input pLow
, pHgh
, dLow
, dHgh);
wire mux;
nmos nl( mux , dLow, pLow);
pmos pl( mux , dLow, pHgh);
nmos nh( mux , dHgh, pHgh);
pmos ph( mux , dHgh, pLow);
Nt t( rslt, mux);
endmodule
module MuOuNmx #( nmBits = 2
, localparam maxBit = nmBits - 1)
( output [ maxBit:0] rslt
, input pHgh
, pLow
, [ maxBit:0] dHgh
, [ maxBit:0] dLow);
genvar bt;
generate
for (bt = 0; bt < nmBits; bt = bt + 1)
begin
Nmx2 m( rslt[ bt], pHgh, pLow, dHgh[ bt], dLow[ bt]);
end
endgenerate
endmodule
module LessThan #( kyBits = 2
, localparam keyHigh = kyBits - 1)
( output rslt
, input [ keyHigh:0] lssr
, [ keyHigh:0] grtr);
assign rslt = lssr < grtr;
endmodule
module sPivots #( kyBits = 2
, nmQueues = 6
, localparam keyHigh = kyBits - 1)
( output chsLf
, chsMd
, chsRg
, [ keyHigh:0] d_hdDm
, [ keyHigh:0] d_hdUm
, input loadingUp
, [ keyHigh:0] hdUl
, [ keyHigh:0] hdUm
, [ keyHigh:0] hdUr
, [ keyHigh:0] hdDl
, [ keyHigh:0] hdDm
, [ keyHigh:0] hdDr);
wire lfLtMd, lfLtRg, mdLtRg;
wire [ keyHigh:0] ntHdLf, ntHdMd, ntHdRg;
wire loadingDown;
wire ntChsLf;
wire mdGeRg;
wire lfGeMd;
wire ldAndLlm;
wire lfGeRg;
wire ldAndLlr;
Nt aT( loadingDown, loadingUp);
Nt bT( mdGeRg, mdLtRg);
generate
if (4 < nmQueues)
begin
MuOuNmx #( kyBits) lMu( ntHdLf, loadingUp, loadingDown, hdDl, hdUl);
MuOuNmx #( kyBits) mMu( ntHdMd, loadingUp, loadingDown, hdDm, hdUm);
assign d_hdDm = hdDm;
assign d_hdUm = hdUm;
LessThan #( kyBits) lmL( lfLtMd, ntHdMd, ntHdLf);
LessThan #( kyBits) lrL( lfLtRg, ntHdRg, ntHdLf);
Nd2 cD( ntChsLf, lfLtMd, lfLtRg);
if (nmQueues == 6)
begin
Nt dT( chsLf, ntChsLf);
Nr2 eR( chsMd, lfLtMd, mdGeRg);
Nr2 fR( chsRg, lfLtRg, mdLtRg);
end
else
begin
Nr2 gR( chsLf, loadingUp, ntChsLf);
Nt hT( lfGeMd, lfLtMd);
Nr2 iR( ldAndLlm, loadingUp, lfGeMd);
Nr2 jR( chsMd, ldAndLlm, mdGeRg);
Nt kT( lfGeRg, lfLtRg);
Nr2 lR( ldAndLlr, loadingUp, lfGeRg);
Nr2 mR( chsRg, ldAndLlr, mdLtRg);
end
end
else
begin
assign chsLf = 1'b0;
Nr2 nR( chsMd, loadingUp, mdGeRg);
Nd2 oD( chsRg, loadingDown, mdLtRg);
end
endgenerate
MuOuNmx #( kyBits) rMu( ntHdRg, loadingUp, loadingDown, hdDr, hdUr);
LessThan #( kyBits) mrL( mdLtRg, ntHdRg, ntHdMd);
endmodule
// if nmQueues == 6 then
// chsLf = ~ ( ~ (lfLtMd & lfLtRg))
// chsMd = ~ (lfLtMd | ~ mdLtRg)
// chsRg = ~ (lfLtRg | mdLtRg)
// else if nmQueues == 5 then
// chsLf = ~ (loadingUp | ~ (lfLtMd & lfLtRg))
// chsMd = ~ (~ (loadingUp | ~ lfLtMd) | ~ mdLtRg)
// chsRg = ~ (~ (loadingUp | ~ lfLtRg) | mdLtRg)
// else if nmQueues == 3 then
// chsLf = 0
// chsMd = ~ (loadingUp | ~ mdLtRg)
// chsRg = ~ (loadingDown & mdLtRg)
Code:
// (c) Kevin Simonson 2025
module t23_sPivots_Bug;
reg ldngUp;
reg [ 1:0] hdUl;
reg [ 1:0] hdUm;
reg [ 1:0] hdUr;
reg [ 1:0] hdDl;
reg [ 1:0] hdDm;
reg [ 1:0] hdDr;
wire chsLf;
wire chsMd;
wire chsRg;
wire [ 1:0] d_hdDm, d_hdUm;
sPivots #( 2, 3)
p( chsLf, chsMd, chsRg
, d_hdDm, d_hdUm
, ldngUp, hdUl, hdUm, hdUr, hdDl, hdDm, hdDr);
initial
begin
ldngUp = 1'b0;
hdUl = 2'b00; hdUm = 2'b10; hdUr = 2'b10;
hdDl = 2'b00; hdDm = 2'b00; hdDr = 2'b00;
#3 $finish;
end
always @( ldngUp, hdUl, hdUm, hdUr, hdDl, hdDm, hdDr, chsLf, chsMd, chsRg)
begin
$display
( "t: %2t, lu: %1b, ul: %2b, um: %2b, ur: %2b, dl: %2b, dm: %2b, dr: %2b"
, $time , ldngUp , hdUl , hdUm , hdUr , hdDl , hdDm , hdDr);
$display( " cl: %1b, cm: %1b, cr: %1b", chsLf, chsMd, chsRg);
$display( "hdDm: %2b, hdUm: %2b", d_hdDm, d_hdUm);
end
endmodule
Code:
Parsing design file 'design.sv'
Parsing design file 'testbench.sv'
Top Level Modules:
t23_sPivots_Bug
TimeScale is 1 ns / 1 ns
Starting vcs inline pass...
1 module and 0 UDP read.
recompiling module t23_sPivots_Bug
rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
if [ -x ../simv ]; then chmod a-x ../simv; fi
g++ -o ../simv -rdynamic -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-rpath=./simv.daidir -Wl,-rpath=/apps/vcsmx/vcs/U-2023.03-SP2/linux64/lib -L/apps/vcsmx/vcs/U-2023.03-SP2/linux64/lib -Wl,-rpath-link=./ objs/amcQw_d.o _331_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative /apps/vcsmx/vcs/U-2023.03-SP2/linux64/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive /apps/vcsmx/vcs/U-2023.03-SP2/linux64/lib/vcs_save_restore_new.o -ldl -lc -lm -lpthread -ldl
../simv up to date
CPU time: .363 seconds to compile + .266 seconds to elab + .296 seconds to link
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 8 19:29 2025
t: 0, lu: 0, ul: 00, um: 10, ur: 10, dl: 00, dm: 00, dr: 00
cl: 0, cm: x, cr: x
hdDm: zz, hdUm: zz
$finish called from file "testbench.sv", line 26.
$finish at simulation time 3
V C S S i m u l a t i o n R e p o r t
Time: 3 ns
CPU Time: 0.350 seconds; Data structure size: 0.0Mb
Sat Feb 8 19:29:34 2025
Done
--- Updated ---
Never mind! I figured out what I was doing wrong.
Last edited:
