can one input clock port be connected to two MMCM for different frequency out?

[skyworld_cy]

Hi,

I'm preparing for one design, which connects two MMCM with one clock input port. The input clock port may work at 125MHz or 200MHz, so two MMCMs are used to generate phase-locked 125MHz or 200MHz separately. Is this kind of connection with MMCMs the right design? If so, how should I set timing constraints? thanks.

 

[dpaul]

@skyworld_cy
Better would be to fix the input clock (speak with the system design engineer if needed), use one MMCM and generate two clocks, 125M and 200M out of it. I am assuming that both 125M and 200M are needed in your design.

 

[FvM]

You might think about using dynamic reconfiguration to switch the MMCM parameters.

An important point not addressed by your question, what's connected downstream of the MMCMs, what do you expect to happen with the MMCM clocked by the "wrong" frequency?

 

[skyworld_cy]

@skyworld_cy
Better would be to fix the input clock (speak with the system design engineer if needed), use one MMCM and generate two clocks, 125M and 200M out of it. I am assuming that both 125M and 200M are needed in your design.

thanks for your kind reply. The system can't be changed.

--- Updated Dec 23, 2022 ---

You might think about using dynamic reconfiguration to switch the MMCM parameters.

An important point not addressed by your question, what's connected downstream of the MMCMs, what do you expect to happen with the MMCM clocked by the "wrong" frequency?

The system is like this: In mode 1, the input clock will be ADC in1 for some design with frequency 125MHz while in the other case, the ADC mode changes to 200MHz.

--- Updated Dec 23, 2022 ---

You might think about using dynamic reconfiguration to switch the MMCM parameters.

An important point not addressed by your question, what's connected downstream of the MMCMs, what do you expect to happen with the MMCM clocked by the "wrong" frequency?

I have tried dynamic reconfiguration before. If this could work, how can I set timing constraints? set the 200MHz as main clock?

 

[FvM]

If I understand right, you are operating the same logic with different frequencies. Means, if you have two separate MMCM, there must be a clock mux between MMCM and logic. I believe that reconfiguring the MMCM would be an approriate solution. Timing constraints for the faster clock should be fine.
It might be even possible that one MMCM configuration works for both clock frequencies. You should check with Xilinx doc and synthesis reports.

 

[skyworld_cy]

If I understand right, you are operating the same logic with different frequencies. Means, if you have two separate MMCM, there must be a clock mux between MMCM and logic. I believe that reconfiguring the MMCM would be an approriate solution. Timing constraints for the faster clock should be fine.
It might be even possible that one MMCM configuration works for both clock frequencies. You should check with Xilinx doc and synthesis reports.

I will check this. Thanks very much